cpu16_alu.sv (902B)
1 // Copyright 2018, Brian Swetland <swetland@frotz.net> 2 // Licensed under the Apache License, Version 2.0. 3 4 `default_nettype none 5 6 module cpu16_alu( 7 input reg [3:0]op, 8 input reg [15:0]x, 9 input reg [15:0]y, 10 output reg [15:0]r 11 ); 12 13 always_comb begin 14 case (op) 15 4'b0000: r = x & y; 16 4'b0001: r = x | y; 17 4'b0010: r = x ^ y; 18 4'b0011: r = ~x; 19 4'b0100: r = x + y; 20 4'b0101: r = x - y; 21 4'b0110: r = { 15'd0, $signed(x) < $signed(y) }; 22 4'b0111: r = { 15'd0, x < y }; 23 4'b1000: r = y[0] ? {x[11:0], 4'b0} : {x[14:0], 1'b0}; // SHL 4 or 1 24 4'b1001: r = y[0] ? {4'b0, x[15:4]} : {1'b0, x[15:1]}; // SHR 4 or 1 25 4'b1010: r = y[0] ? {x[11:0], x[15:12]} : {x[14:0], x[15]}; // ROL 4 or 1 26 4'b1011: r = y[0] ? {x[3:0], x[15:4]} : {x[0], x[15:1]}; // ROR 4 or 1 27 4'b1100: r = x * y; 28 4'b1101: r = { x[7:0], y[7:0] }; 29 4'b1110: r = { x[7:0], y[15:8] }; 30 4'b1111: r = { y[5:0], x[9:0] }; 31 endcase 32 end 33 34 endmodule