cpu16_regs.sv (1323B)
1 // Copyright 2018, Brian Swetland <swetland@frotz.net> 2 // Licensed under the Apache License, Version 2.0. 3 4 `default_nettype none 5 6 module cpu16_regs( 7 input clk, 8 input [2:0]asel, 9 input [2:0]bsel, 10 input [2:0]wsel, 11 input wreg, 12 input [15:0]wdata, 13 output [15:0]adata, 14 output [15:0]bdata 15 ); 16 17 `ifdef verilator 18 reg [15:0]rmem[0:7]; 19 reg [15:0]areg; 20 reg [15:0]breg; 21 22 always_ff @(negedge clk) begin 23 if (wreg) 24 rmem[wsel] <= wdata; 25 end 26 always_ff @(posedge clk) begin 27 areg <= rmem[asel]; 28 breg <= rmem[bsel]; 29 end 30 31 assign adata = areg; 32 assign bdata = breg; 33 `else 34 `ifdef YOSYS 35 SB_RAM40_4K #( 36 .READ_MODE(0), 37 .WRITE_MODE(0) 38 ) 39 `else 40 SB_RAM256x16 41 `endif 42 bank_a ( 43 .WADDR(wsel), 44 .RADDR(asel), 45 .MASK(16'b0), 46 .WDATA(wdata), 47 .RDATA(adata), 48 .WE(1'b1), 49 .WCLKE(wreg), 50 .WCLK(clk), 51 .RE(1'b1), 52 .RCLKE(1'b1), 53 .RCLK(clk) 54 ); 55 56 `ifdef YOSYS 57 SB_RAM40_4K #( 58 .READ_MODE(0), 59 .WRITE_MODE(0) 60 ) 61 `else 62 SB_RAM256x16 63 `endif 64 bank_b ( 65 .WADDR(wsel), 66 .RADDR(bsel), 67 .MASK(16'b0), 68 .WDATA(wdata), 69 .RDATA(bdata), 70 .WE(1'b1), 71 .WCLKE(wreg), 72 .WCLK(clk), 73 .RE(1'b1), 74 .RCLKE(1'b1), 75 .RCLK(clk) 76 ); 77 `endif 78 79 endmodule 80 81