isa16v5.txt (2063B)
1 instruction encodings alu opcodes 2 ---------------------------------------------- --------------------------- 3 FEDC BA9 876 543 210 4 ffff bbb aaa ccc 000 ALU Rc, Ra, Rb 0000 AND r = x & y 5 siii iii aaa ccc 001 ADD Rc, Ra, si7 0001 ORR r = x | y 6 siii iii jjj ccc 010 MOV Rc, si10 0010 XOR r = x ^ y 7 siii iii aaa ccc 011 LW Rc, [Ra, si7] 0011 NOT r = ~x 8 siii iii zjj bbb 100 BZ/BNZ Rb, si9 0100 ADD r = x + y 9 siii iii aaa bbb 101 SW Rb, [Ra, si7] 0101 SUB r = x - y 10 siii iii jjj kkl 110 B/BL si12 0110 SLT r = x < y (signed) 11 0xxx 000 aaa xxl 111 B/BL Ra 0111 SLU r = x < y (unsigned) 12 0xxx 001 xxx xxx 111 NOP 1000 SHL 1|4 13 0 010 111 1001 SHR 1|4 14 0 011 111 1010 ROL 1|4 15 0uuu 100 uuu ccc 111 LC Rc, u6 1011 ROR 1|4 16 0uuu 101 uuu bbb 111 SC Rb, u6 1100 MUL r = x * y 17 0xff 110 aaa ccc 111 SHL/SHR/ROL/ROR Rc, Ra, 1 1101 DUP r = {x[7:0], y[7:0]} 18 0xff 111 aaa ccc 111 SHL/SHR/ROL/ROR Rc, Ra, 4 1110 SWP r = {x[7:0], y[15:8]} 19 1iii iii aaa ccc 111 MHI Rc, Ra, si7[5:0] 1111 MHI r = {y[5:0], x[9:0]} 20 21 aliases immediate forms (shared bits) 22 ----------------------------------- ------------------------------- 23 MOV Rc, Ra -> AND Rc, Ra, Ra si7 siiiiiixxxxxxxxx -> ssssssssssiiiiii 24 SNE Rc, Ra, Rb -> XOR Rc, Ra, Rb si9 siiiiiixjjxxxxxx -> ssssssssjjiiiiii 25 SGE Rc, Ra, Rb -> SLT Rc, Rb, Ra si10 siiiiiijjjxxxxxx -> sssssssjjjiiiiii 26 SGU Rc, Ra, Rb -> SLU Rc, Rb, Ra si12 siiiiiijjjkkxxxx -> ssssskkjjjiiiiii 27 28 ir[2:0] x00=si9 xx1=si7 010=si10 110=si12 29 30 some implementation notes 31 ------------------------- 32 alu.x = regs.a | pc (b) 33 alu.y = regs.b | imm 34 alu.op = ffff | 00ff(shifts) | 0100(lw/sw/b) | 1111 (mhi) 35 brtgt = regs.a | alu.r 36 bsel = ir[2] ? ir[2:0] : ir[11:9] 37 wsel = ir[5:3] | 7 (bl) 38