testbench.sv (1749B)
1 // Copyright 2018, Brian Swetland <swetland@frotz.net> 2 // Licensed under the Apache License, Version 2.0. 3 4 `default_nettype none 5 6 `timescale 1ns / 1ps 7 8 module testbench( 9 input clk 10 ); 11 12 reg [15:0]count = 16'd0; 13 reg reset = 1'b0; 14 15 reg burp = 1'b0; 16 17 always @(posedge clk) begin 18 count <= count + 16'd1; 19 // burp <= (count >= 16'd0010) && (count <= 16'd0012) ? 1'b1 : 1'b0; 20 if (count == 16'd0005) reset <= 1'b0; 21 if (count == 16'd1000) $finish; 22 if (cpu.de_ir == 16'hFFFF) begin 23 for ( integer i = 0; i < 8; i++ ) begin 24 $display(":REG R%0d %8X", i, cpu.regs.rmem[i]); 25 end 26 $display(":END"); 27 $finish; 28 end 29 end 30 31 wire [15:0]ins_rd_addr; 32 wire [15:0]ins_rd_data; 33 wire ins_rd_req; 34 35 wire [15:0]dat_rw_addr; 36 wire [15:0]dat_rd_data; 37 wire dat_rd_req; 38 wire [15:0]dat_wr_data; 39 wire dat_wr_req; 40 41 reg ins_rd_rdy = 1'b0; 42 reg dat_rd_rdy = 1'b0; 43 reg dat_wr_rdy = 1'b0; 44 45 always_ff @(posedge clk) begin 46 if (reset) begin 47 ins_rd_rdy <= 1'b0; 48 dat_rd_rdy <= 1'b0; 49 dat_wr_rdy <= 1'b0; 50 end else begin 51 ins_rd_rdy <= ins_rd_req; 52 dat_rd_rdy <= dat_rd_req; 53 dat_wr_rdy <= dat_wr_req; 54 end 55 end 56 57 simram ins_ram( 58 .clk(clk), 59 .waddr(16'd0), 60 .wdata(16'd0), 61 .we(1'd0), 62 .raddr(ins_rd_addr), 63 .rdata(ins_rd_data), 64 .re(1'd1) 65 ); 66 67 simram dat_ram( 68 .clk(clk), 69 .waddr(dat_rw_addr), 70 .wdata(dat_wr_data), 71 .we(dat_wr_req), 72 .raddr(dat_rw_addr), 73 .rdata(dat_rd_data), 74 .re(dat_rd_req) 75 ); 76 77 cpu16 cpu( 78 .clk(clk), 79 .ins_rd_addr(ins_rd_addr), 80 .ins_rd_data(burp ? 16'hEEEE : ins_rd_data), 81 .ins_rd_req(ins_rd_req), 82 .ins_rd_rdy(ins_rd_rdy & ~burp), 83 84 .dat_rw_addr(dat_rw_addr), 85 .dat_wr_data(dat_wr_data), 86 .dat_rd_data(dat_rd_data), 87 .dat_rd_req(dat_rd_req), 88 .dat_rd_rdy(dat_rd_rdy), 89 .dat_wr_req(dat_wr_req), 90 .dat_wr_rdy(dat_wr_rdy), 91 92 .reset(reset) 93 ); 94 95 endmodule