gateware

A collection of little open source FPGA hobby projects
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crc8_serial.sv (669B)


      1 // Copyright 2018, Brian Swetland <swetland@frotz.net>
      2 // Licensed under the Apache License, Version 2.0.
      3 
      4 `default_nettype none
      5 
      6 // 0x9C 10011100x // koopman notation (low bit implied)
      7 // 0x39 x00111001 // truncated notation (high bit implied)
      8 
      9 module crc8_serial(
     10 	input clk,
     11 	input din,
     12 	input en,
     13 	input rst,
     14 	output [7:0]crc
     15 	);
     16 
     17 reg [7:0]r;
     18 
     19 wire d = din ^ r[7];
     20 
     21 always @(posedge clk) begin
     22 	if (rst) begin
     23 		r <= 8'hFF;
     24 	end else if (en) begin
     25 		r[0] <= d;
     26 		r[1] <= r[0];
     27 		r[2] <= r[1];
     28 		r[3] <= r[2] ^ d;
     29 		r[4] <= r[3] ^ d;
     30 		r[5] <= r[4] ^ d;
     31 		r[6] <= r[5];
     32 		r[7] <= r[6];
     33 	end
     34 end
     35 
     36 assign crc = { r[0],r[1],r[2],r[3],r[4],r[5],r[6],r[7] };
     37 
     38 endmodule
     39