gateware

A collection of little open source FPGA hobby projects
git clone http://frotz.net/git/gateware.git
Log | Files | Refs | README

dvi-backend.sv (2006B)


      1 // Copyright 2014, Brian Swetland <swetland@frotz.net>
      2 // Licensed under the Apache License, Version 2.0.
      3 
      4 `default_nettype none
      5 
      6 module dvi_backend (
      7 	input pixclk,
      8 	input pixclk5x,
      9 
     10 	// TMDS33 outputs at pixclk5x DDR
     11 	output wire [3:0]pin_dvi_dp,
     12 	output wire [3:0]pin_dvi_dn,
     13 
     14 	// RGB data input at pixclk
     15 	input wire hsync,
     16 	input wire vsync,
     17 	input wire active,
     18 	input wire [7:0]red,
     19 	input wire [7:0]grn,
     20 	input wire [7:0]blu
     21 	);
     22 
     23 wire [3:0]dvi_dp;
     24 wire [3:0]dvi_dn;
     25 
     26 wire [9:0] ch0, ch1, ch2;
     27 
     28 reg [9:0]ch3 = 10'b0000011111;
     29 
     30 dvi_encoder enc2(
     31 	.clk(pixclk),
     32 	.din(red),
     33 	.ctrl(0),
     34 	.active(active),
     35 	.dout(ch2));
     36 
     37 dvi_encoder enc1(
     38 	.clk(pixclk),
     39 	.active(active),
     40 	.din(grn),
     41 	.ctrl(0),
     42 	.dout(ch1));
     43 
     44 dvi_encoder enc0(
     45 	.clk(pixclk),
     46 	.active(active),
     47 	.din(blu),
     48 	.ctrl({vsync,hsync}),
     49 	.dout(ch0));
     50 
     51 // shift registers
     52 reg [9:0]ch0s;
     53 reg [9:0]ch1s;
     54 reg [9:0]ch2s;
     55 reg [9:0]ch3s;
     56 
     57 reg [4:0]cycle = 5'b00001;
     58 
     59 // TODO ideally cycle[0] would occur on the 4th
     60 // pixclk5x tick within every pixclk
     61 //
     62 always_ff @(posedge pixclk5x) begin
     63 	cycle <= { cycle[0], cycle[4:1] };
     64 	ch0s <= cycle[0] ? ch0 : { 2'b0, ch0s[9:2] };
     65 	ch1s <= cycle[0] ? ch1 : { 2'b0, ch1s[9:2] };
     66 	ch2s <= cycle[0] ? ch2 : { 2'b0, ch2s[9:2] };
     67 	ch3s <= cycle[0] ? ch3 : { 2'b0, ch3s[9:2] };
     68 end
     69 
     70 dvi_ddr_out ddo0 (
     71 	.clk(pixclk5x),
     72 	.din(ch0s[1:0]),
     73 	.pin_dp(pin_dvi_dp[0]),
     74 	.pin_dn(pin_dvi_dn[0]));
     75 
     76 dvi_ddr_out ddo1 (
     77 	.clk(pixclk5x),
     78 	.din(ch1s[1:0]),
     79 	.pin_dp(pin_dvi_dp[1]),
     80 	.pin_dn(pin_dvi_dn[1]));
     81 
     82 dvi_ddr_out ddo2 (
     83 	.clk(pixclk5x),
     84 	.din(ch2s[1:0]),
     85 	.pin_dp(pin_dvi_dp[2]),
     86 	.pin_dn(pin_dvi_dn[2]));
     87 
     88 dvi_ddr_out ddo3 (
     89 	.clk(pixclk5x),
     90 	.din(ch3s[1:0]),
     91 	.pin_dp(pin_dvi_dp[3]),
     92 	.pin_dn(pin_dvi_dn[3]));
     93 
     94 endmodule
     95 
     96 module dvi_ddr_out(
     97 	input wire clk,
     98 	input wire [1:0]din,
     99 	output wire pin_dp,
    100 	output wire pin_dn
    101 );
    102 
    103 `ifndef verilator
    104 ODDRX1F dp(
    105 	.D0(din[0]),
    106 	.D1(din[1]),
    107 	.Q(pin_dp),
    108 	.SCLK(clk),
    109 	.RST(0));
    110 
    111 ODDRX1F dn(
    112 	.D0(~din[0]),
    113 	.D1(~din[1]),
    114 	.Q(pin_dn),
    115 	.SCLK(clk),
    116 	.RST(0));
    117 `endif
    118 
    119 endmodule
    120