dvi-encoder.sv (1848B)
1 // Copyright 2014, Brian Swetland <swetland@frotz.net> 2 // Licensed under the Apache License, Version 2.0. 3 4 `default_nettype none 5 6 module dvi_encoder( 7 input wire clk, 8 input wire active, 9 input wire [7:0]din, 10 input wire [1:0]ctrl, 11 output reg [9:0]dout 12 ); 13 14 reg [3:0]acc = 0; 15 16 wire [8:0]xo; 17 wire [8:0]xn; 18 19 assign xn[0] = din[0]; 20 assign xn[1] = din[1] ~^ xn[0]; 21 assign xn[2] = din[2] ~^ xn[1]; 22 assign xn[3] = din[3] ~^ xn[2]; 23 assign xn[4] = din[4] ~^ xn[3]; 24 assign xn[5] = din[5] ~^ xn[4]; 25 assign xn[6] = din[6] ~^ xn[5]; 26 assign xn[7] = din[7] ~^ xn[6]; 27 assign xn[8] = 0; 28 29 assign xo[0] = din[0]; 30 assign xo[1] = din[1] ^ xo[0]; 31 assign xo[2] = din[2] ^ xo[1]; 32 assign xo[3] = din[3] ^ xo[2]; 33 assign xo[4] = din[4] ^ xo[3]; 34 assign xo[5] = din[5] ^ xo[4]; 35 assign xo[6] = din[6] ^ xo[5]; 36 assign xo[7] = din[7] ^ xo[6]; 37 assign xo[8] = 1; 38 39 localparam Z3 = 3'd0; 40 41 wire [3:0]ones = 42 {Z3,din[0]} + {Z3,din[1]} + {Z3,din[2]} + 43 {Z3,din[3]} + {Z3,din[4]} + {Z3,din[5]} + 44 {Z3,din[6]} + {Z3,din[7]}; 45 46 wire use_xn = ((ones > 4) | ((ones == 4) & (din[0] == 0))); 47 48 wire [8:0]tmp = use_xn ? xn : xo; 49 wire [3:0]tmp_ones = 50 {Z3,tmp[0]} + {Z3,tmp[1]} + {Z3,tmp[2]} + 51 {Z3,tmp[3]} + {Z3,tmp[4]} + {Z3,tmp[5]} + 52 {Z3,tmp[6]} + {Z3,tmp[7]}; 53 54 wire no_bias = (acc == 0) | (tmp_ones == 4); 55 56 wire same_sign = (acc[3] == tmp_ones[3]); 57 58 wire inv = no_bias ? (~tmp[8]) : same_sign; 59 60 wire [9:0]enc = { inv, tmp[8], inv ? ~tmp[7:0] : tmp[7:0] }; 61 62 always @(posedge clk) begin 63 if (active) begin 64 dout <= enc; 65 acc <= acc - 5 + {Z3,enc[0]} + {Z3,enc[1]} + 66 {Z3,enc[2]} + {Z3,enc[3]} + {Z3,enc[4]} + 67 {Z3,enc[5]} + {Z3,enc[6]} + {Z3,enc[7]} + 68 {Z3,enc[8]} + {Z3,enc[9]}; 69 end else begin 70 case (ctrl) 71 2'b00: dout <= 10'b1101010100; 72 2'b01: dout <= 10'b0010101011; 73 2'b10: dout <= 10'b0101010100; 74 2'b11: dout <= 10'b1010101011; 75 endcase 76 acc <= 0; 77 end 78 end 79 80 endmodule