gateware

A collection of little open source FPGA hobby projects
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testbench.sv (618B)


      1 // Copyright 2015, Brian Swetland <swetland@frotz.net>
      2 // Licensed under the Apache License, Version 2.0.
      3 
      4 `default_nettype none
      5 
      6 `timescale 1ns / 1ps
      7 
      8 `define HEX_PATHS
      9 
     10 module testbench(
     11         input clk,
     12 	output [3:0]vga_red,
     13 	output [3:0]vga_grn,
     14 	output [3:0]vga_blu,
     15 	output vga_hsync,
     16 	output vga_vsync,
     17 	output vga_frame,
     18 	output reg error = 0,
     19 	output reg done = 0
     20         );
     21 
     22 display #(
     23 	.BPP(4),
     24 	)vga(
     25 	.clk(clk),
     26 	.red(vga_red),
     27 	.grn(vga_grn),
     28 	.blu(vga_blu),
     29 	.hsync(vga_hsync),
     30 	.vsync(vga_vsync),
     31 	.frame(vga_frame),
     32 	.active(),
     33 	.waddr(12'b0),
     34 	.wdata(16'b0),
     35 	.we(1'b0),
     36 	.wclk(clk)
     37 	);
     38 
     39 endmodule