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eth_crc32_test.sv (1988B)


      1 // Copyright 2018, Brian Swetland <swetland@frotz.net>
      2 // Licensed under the Apache License, Version 2.0.
      3 
      4 `default_nettype none
      5 
      6 module testbench(
      7 	input clk,
      8 	output reg error = 0,
      9 	output reg done = 0
     10 );
     11 
     12 reg [8:0]packet[0:103];
     13 
     14 initial $readmemh("hdl/ethernet/eth_crc32_testpacket.hex", packet);
     15 
     16 reg [6:0]pktcount = 7'd0;
     17 reg rst = 1'b1;
     18 reg wr = 1'b0;
     19 reg [7:0]pktdata = 8'd0;
     20 reg pktdone = 1'b0;
     21 wire [31:0]crc0;
     22 wire [31:0]crc1;
     23 
     24 `ifdef BYTEWISE
     25 eth_crc32_8(
     26 	.clk(clk),
     27 	.en(wr & ~pktdone),
     28 	.rst(rst),
     29 	.din(pktdata),
     30 	.crc(crc0)
     31 );
     32 
     33 always_ff @(posedge clk) begin
     34 	rst <= 1'b0;
     35 	wr <= 1'b1;
     36 	if (~pktdone)
     37 		{ pktdone, pktdata } <= packet[pktcount];
     38 	pktcount <= pktcount + 7'd1;
     39 	$display("WR=", wr, " DONE=", pktdone, " IDX=", pktcount, " DATA=", pktdata, " CRC=", crc0, " NOT=", ~crc0);
     40 	if (pktdone) begin
     41 		if(crc0 == 32'hdebb20e3) begin
     42 			$display("SUCCESS");
     43 			done <= 1;
     44 		end else begin
     45 			$display("FAILURE");
     46 			error <= 1;
     47 		end
     48 		done <= 1;
     49 	end
     50 	if (pktcount == 105) error <= 1;
     51 end
     52 `else
     53 reg [3:0]tick = 4'b0001;
     54 
     55 eth_crc32_2 ethcrc0(
     56 	.clk(clk),
     57 	.en(wr & ~pktdone),
     58 	.rst(rst),
     59 	.din(pktdata[1:0]),
     60 	.crc(crc0)
     61 );
     62 
     63 eth_crc32_8 ethcrc1(
     64 	.clk(clk),
     65 	.en(tick[3] & ~pktdone),
     66 	.rst(rst),
     67 	.din(pktdata),
     68 	.crc(crc1)
     69 );
     70 
     71 always_ff @(posedge clk) begin
     72 	rst <= 1'b0;
     73 	wr <= 1'b1;
     74 	if (~pktdone) begin
     75 		if (tick[0]) begin
     76 			{ pktdone, pktdata } <= packet[pktcount];
     77 			pktcount <= pktcount + 7'd1;
     78 		end else begin
     79 			{ pktdone, pktdata } <= { pktdone, 2'b0, pktdata[7:2] };
     80 		end
     81 		tick <= { tick[0], tick[3:1] };
     82 	end
     83 	$display("WR=", wr, " DONE=", pktdone, " IDX=", pktcount, " DATA=", pktdata, " CRCx2=", crc0, " CRCx8=", crc1, " NOT=", ~crc1);
     84 	if (pktdone) begin
     85 		if (crc0 != 32'hdebb20e3) begin
     86 			$display("CRC32x2 FAILED");
     87 			error <= 1;
     88 		end else if (crc1 != 32'hdebb20e3) begin
     89 			$display("CRC32x8 FAILED");
     90 			error <= 1;
     91 		end else begin
     92 			$display("SUCCESS");
     93 			done <= 1;
     94 		end
     95 	end
     96 	if (pktcount == 105) error <= 1;
     97 end
     98 `endif
     99 
    100 endmodule