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eth_rgmii_rx_glue_ecp5.sv (985B)

      1 // Copyright 2020 Brian Swetland <swetland@frotz.net>
      2 // Licensed under the Apache License, Version 2.0.
      3 
      4 `default_nettype none
      5 
      6 module eth_rgmii_rx_glue (
      7 	input wire rx_clk,
      8 	input wire pin_rx_dv,
      9 	input wire [3:0]pin_rx_data,
     10 	output wire rx_dv,
     11 	output wire rx_err,
     12 	output wire [7:0]rx_data
     13 );
     14 
     15 `ifndef verilator
     16 wire delay_rx_dv;
     17 wire [3:0]delay_rx_data;
     18 
     19 DELAYF #(
     20 	.DEL_MODE("SCLK_CENTERED"),
     21 	.DEL_VALUE(80) // units of ~25ps
     22 	) ctrl_delay (
     23 	.LOADN(1),
     24 	.MOVE(0),
     25 	.DIRECTION(0),
     26 	.A(pin_rx_dv),
     27 	.Z(delay_rx_dv)
     28 );
     29 IDDRX1F ctrl_ddr (
     30 	.D(delay_rx_dv),
     31 	.SCLK(rx_clk),
     32 	.RST(0),
     33 	.Q0(rx_dv),
     34 	.Q1(rx_err)
     35 );
     36 
     37 genvar i;
     38 
     39 generate for (i = 0; i < 4; i++) begin
     40 DELAYF #(
     41 	.DEL_MODE("SCLK_CENTERED"),
     42 	.DEL_VALUE(80) // units of ~25ps
     43 	) data_delay (
     44 	.LOADN(1),
     45 	.MOVE(0),
     46 	.DIRECTION(0),
     47 	.A(pin_rx_data[i]),
     48 	.Z(delay_rx_data[i])
     49 );
     50 IDDRX1F data_ddr (
     51 	.D(delay_rx_data[i]),
     52 	.SCLK(rx_clk),
     53 	.RST(0),
     54 	.Q0(rx_data[i]),
     55 	.Q1(rx_data[i+4])
     56 );
     57 end endgenerate
     58 `endif
     59 
     60 endmodule