eth_rgmii_tx_glue_ecp5.sv (1326B)
1 // Copyright 2020 Brian Swetland <swetland@frotz.net> 2 // Licensed under the Apache License, Version 2.0. 3 4 `default_nettype none 5 6 module eth_rgmii_tx_glue ( 7 input wire tx_clk, 8 output wire pin_tx_clk, 9 output wire pin_tx_en, 10 output wire [3:0]pin_tx_data, 11 input wire tx_en, 12 input wire tx_err, 13 input wire [7:0]tx_data 14 ); 15 16 `ifndef verilator 17 wire delay_tx_clk; 18 wire delay_tx_en; 19 wire delay_tx_err; 20 wire [3:0]delay_tx_data; 21 22 DELAYF #( 23 .DEL_MODE("SCLK_CENTERED"), 24 .DEL_VALUE(0) // units of ~25ps 25 ) clock_delay ( 26 .LOADN(1), 27 .MOVE(0), 28 .DIRECTION(0), 29 .A(delay_tx_clk), 30 .Z(pin_tx_clk) 31 ); 32 ODDRX1F clock_ddr ( 33 //.Q(delay_tx_clk), 34 .Q(delay_tx_clk), 35 .SCLK(tx_clk), 36 .RST(0), 37 .D0(1), 38 .D1(0) 39 ); 40 41 DELAYF #( 42 .DEL_MODE("SCLK_CENTERED"), 43 .DEL_VALUE(0) // units of ~25ps 44 ) ctrl_delay ( 45 .LOADN(1), 46 .MOVE(0), 47 .DIRECTION(0), 48 .A(delay_tx_en), 49 .Z(pin_tx_en) 50 ); 51 ODDRX1F ctrl_ddr ( 52 .Q(delay_tx_en), 53 .SCLK(tx_clk), 54 .RST(0), 55 .D0(tx_en), 56 .D1(tx_err ^ tx_en) 57 ); 58 59 genvar i; 60 61 generate for (i = 0; i < 4; i++) begin 62 DELAYF #( 63 .DEL_MODE("SCLK_CENTERED"), 64 .DEL_VALUE(0) // units of ~25ps 65 ) data_delay ( 66 .LOADN(1), 67 .MOVE(0), 68 .DIRECTION(0), 69 .A(delay_tx_data[i]), 70 .Z(pin_tx_data[i]) 71 ); 72 ODDRX1F data_ddr ( 73 .Q(delay_tx_data[i]), 74 .SCLK(tx_clk), 75 .RST(0), 76 .D0(tx_data[i]), 77 .D1(tx_data[i+4]) 78 ); 79 end endgenerate 80 `endif 81 82 endmodule