icebreaker_hdmi111.sv (1407B)
1 // Copyright 2018, Brian Swetland <swetland@frotz.net> 2 // Licensed under the Apache License, Version 2.0. 3 4 `default_nettype none 5 6 module top( 7 input clk12m_in, 8 output hdmi_red, 9 output hdmi_grn, 10 output hdmi_blu, 11 output hdmi_hsync, 12 output hdmi_vsync, 13 output hdmi_de, 14 output hdmi_clk, 15 input uart_rx, 16 output uart_tx, 17 output led_red, 18 output led_grn 19 ); 20 21 wire clk12m; 22 wire clk25m; 23 24 pll_12_25 pll0 ( 25 .clk12m_in(clk12m_in), 26 .clk12m_out(clk12m), 27 .clk25m_out(clk25m), 28 .lock(), 29 .reset(1'b1) 30 ); 31 32 `ifdef verilator 33 assign hdmi_clk = clk25m; 34 `else 35 SB_IO #( 36 .PIN_TYPE(6'b010000), // DDR OUTPUT 37 .PULLUP(1'b0), 38 .NEG_TRIGGER(1'b0), 39 .IO_STANDARD("SB_LVCMOS") 40 ) hdmi_clk_io ( 41 .PACKAGE_PIN(hdmi_clk), 42 .LATCH_INPUT_VALUE(), 43 .CLOCK_ENABLE(), // per docs, leave discon for always enable 44 .INPUT_CLK(), 45 .OUTPUT_CLK(clk25m), 46 .D_OUT_0(1'b1), 47 .D_OUT_1(1'b0), 48 .D_IN_0(), 49 .D_IN_1() 50 ); 51 `endif 52 53 wire [15:0]dbg_wdata; 54 wire [15:0]dbg_waddr; 55 wire dbg_we; 56 57 display #( 58 .BPP(1), 59 ) display0 ( 60 .clk(clk25m), 61 .red(hdmi_red), 62 .grn(hdmi_grn), 63 .blu(hdmi_blu), 64 .hsync(hdmi_hsync), 65 .vsync(hdmi_vsync), 66 .active(hdmi_de), 67 .frame(), 68 .wclk(clk25m), 69 .waddr(dbg_waddr[11:0]), 70 .wdata(dbg_wdata[15:0]), 71 .we(dbg_we) 72 ); 73 74 uart_debug_ifc uart( 75 .sys_clk(clk12m), 76 .sys_wr(dbg_we), 77 .sys_waddr(dbg_waddr), 78 .sys_wdata(dbg_wdata), 79 .uart_rx(uart_rx), 80 .uart_tx(uart_tx), 81 .led_red(led_red), 82 .led_grn(led_grn) 83 ); 84 85 endmodule