ecp5_pll_12_25.v (1454B)
1 // $ ecppll -f pll.v -i 12.0 -o 25.0 --clkin_name clk12m_in --clkout0_name clk25m_out 2 // 3 // diamond 3.7 accepts this PLL 4 // diamond 3.8-3.9 is untested 5 // diamond 3.10 or higher is likely to abort with error about unable to use feedback signal 6 // cause of this could be from wrong CPHASE/FPHASE parameters 7 module pll_12_25 8 ( 9 input clk12m_in, // 12 MHz, 0 deg 10 output clk25m_out, // 24 MHz, 0 deg 11 output locked 12 ); 13 14 `ifndef verilator 15 (* FREQUENCY_PIN_CLKI="12" *) 16 (* FREQUENCY_PIN_CLKOP="24" *) 17 (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) 18 EHXPLLL #( 19 .PLLRST_ENA("DISABLED"), 20 .INTFB_WAKE("DISABLED"), 21 .STDBY_ENABLE("DISABLED"), 22 .DPHASE_SOURCE("DISABLED"), 23 .OUTDIVIDER_MUXA("DIVA"), 24 .OUTDIVIDER_MUXB("DIVB"), 25 .OUTDIVIDER_MUXC("DIVC"), 26 .OUTDIVIDER_MUXD("DIVD"), 27 .CLKI_DIV(1), 28 .CLKOP_ENABLE("ENABLED"), 29 .CLKOP_DIV(25), 30 .CLKOP_CPHASE(12), 31 .CLKOP_FPHASE(0), 32 .FEEDBK_PATH("CLKOP"), 33 .CLKFB_DIV(2) 34 ) pll_i ( 35 .RST(1'b0), 36 .STDBY(1'b0), 37 .CLKI(clk12i), 38 .CLKOP(clk25o), 39 .CLKFB(clk25o), 40 .CLKINTFB(), 41 .PHASESEL0(1'b0), 42 .PHASESEL1(1'b0), 43 .PHASEDIR(1'b1), 44 .PHASESTEP(1'b1), 45 .PHASELOADREG(1'b1), 46 .PLLWAKESYNC(1'b0), 47 .ENCLKOP(1'b0), 48 .LOCK(locked) 49 ); 50 `endif 51 52 endmodule