gateware

A collection of little open source FPGA hobby projects
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ecp5_pll_25_100.v (1378B)


      1 // diamond 3.7 accepts this PLL
      2 // diamond 3.8-3.9 is untested
      3 // diamond 3.10 or higher is likely to abort with error about unable to use feedback signal
      4 // cause of this could be from wrong CPHASE/FPHASE parameters
      5 module pll_25_100
      6 (
      7     input clk25m_in, // 25 MHz, 0 deg
      8     output clk100m_out, // 100 MHz, 0 deg
      9     output locked
     10 );
     11 `ifndef verilator
     12 (* FREQUENCY_PIN_CLKI="25" *)
     13 (* FREQUENCY_PIN_CLKOP="100" *)
     14 (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
     15 EHXPLLL #(
     16         .PLLRST_ENA("DISABLED"),
     17         .INTFB_WAKE("DISABLED"),
     18         .STDBY_ENABLE("DISABLED"),
     19         .DPHASE_SOURCE("DISABLED"),
     20         .OUTDIVIDER_MUXA("DIVA"),
     21         .OUTDIVIDER_MUXB("DIVB"),
     22         .OUTDIVIDER_MUXC("DIVC"),
     23         .OUTDIVIDER_MUXD("DIVD"),
     24         .CLKI_DIV(1),
     25         .CLKOP_ENABLE("ENABLED"),
     26         .CLKOP_DIV(6),
     27         .CLKOP_CPHASE(2),
     28         .CLKOP_FPHASE(0),
     29         .FEEDBK_PATH("CLKOP"),
     30         .CLKFB_DIV(4)
     31     ) pll_i (
     32         .RST(1'b0),
     33         .STDBY(1'b0),
     34         .CLKI(clk25m_in),
     35         .CLKOP(clk100m_out),
     36         .CLKFB(clk100m_out),
     37         .CLKINTFB(),
     38         .PHASESEL0(1'b0),
     39         .PHASESEL1(1'b0),
     40         .PHASEDIR(1'b1),
     41         .PHASESTEP(1'b1),
     42         .PHASELOADREG(1'b1),
     43         .PLLWAKESYNC(1'b0),
     44         .ENCLKOP(1'b0),
     45         .LOCK(locked)
     46 	);
     47 `endif
     48 endmodule