ecp5_pll_25_125_250.v (1637B)
1 // $ ecppll -i 25 -o 250 --clkout1 125 2 // diamond 3.7 accepts this PLL 3 // diamond 3.8-3.9 is untested 4 // diamond 3.10 or higher is likely to abort with error about unable to use feedback signal 5 // cause of this could be from wrong CPHASE/FPHASE parameters 6 module pll_25_125_250 7 ( 8 input clk25m_in, // 25 MHz, 0 deg 9 output clk250m_out, // 250 MHz, 0 deg 10 output clk125m_out, // 125 MHz, 0 deg 11 output locked 12 ); 13 14 `ifndef verilator 15 (* FREQUENCY_PIN_CLKI="25" *) 16 (* FREQUENCY_PIN_CLKOP="250" *) 17 (* FREQUENCY_PIN_CLKOS="125" *) 18 (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) 19 EHXPLLL #( 20 .PLLRST_ENA("DISABLED"), 21 .INTFB_WAKE("DISABLED"), 22 .STDBY_ENABLE("DISABLED"), 23 .DPHASE_SOURCE("DISABLED"), 24 .OUTDIVIDER_MUXA("DIVA"), 25 .OUTDIVIDER_MUXB("DIVB"), 26 .OUTDIVIDER_MUXC("DIVC"), 27 .OUTDIVIDER_MUXD("DIVD"), 28 .CLKI_DIV(1), 29 .CLKOP_ENABLE("ENABLED"), 30 .CLKOP_DIV(2), 31 .CLKOP_CPHASE(0), 32 .CLKOP_FPHASE(0), 33 .CLKOS_ENABLE("ENABLED"), 34 .CLKOS_DIV(4), 35 .CLKOS_CPHASE(0), 36 .CLKOS_FPHASE(0), 37 .FEEDBK_PATH("CLKOP"), 38 .CLKFB_DIV(10) 39 ) pll_i ( 40 .RST(1'b0), 41 .STDBY(1'b0), 42 .CLKI(clk25m_in), 43 .CLKOP(clk250m_out), 44 .CLKOS(clk125m_out), 45 .CLKFB(clk250m_out), 46 .CLKINTFB(), 47 .PHASESEL0(1'b0), 48 .PHASESEL1(1'b0), 49 .PHASEDIR(1'b1), 50 .PHASESTEP(1'b1), 51 .PHASELOADREG(1'b1), 52 .PLLWAKESYNC(1'b0), 53 .ENCLKOP(1'b0), 54 .LOCK(locked) 55 ); 56 `endif 57 58 endmodule