gateware

A collection of little open source FPGA hobby projects
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pll_12_25.v (1342B)

      1 `default_nettype none
      2 
      3 module pll_12_25(
      4 	input clk12m_in,
      5 	output clk12m_out,
      6 	output clk25m_out,
      7 	input reset,
      8 	output lock
      9 	);
     10 
     11 `ifndef verilator
     12 
     13 // generated by icecube2 wizard
     14 SB_PLL40_2_PAD pll_inst(.PACKAGEPIN(clk12m_in),
     15                         .PLLOUTCOREA(),
     16                         .PLLOUTCOREB(),
     17                         .PLLOUTGLOBALA(clk12m_out),
     18                         .PLLOUTGLOBALB(clk25m_out),
     19                         .EXTFEEDBACK(),
     20                         .DYNAMICDELAY(),
     21                         .RESETB(reset),
     22                         .BYPASS(1'b0),
     23                         .LATCHINPUTVALUE(),
     24                         .LOCK(lock),
     25                         .SDI(),
     26                         .SDO(),
     27                         .SCLK());
     28 
     29 //\\ Fin=12, Fout=25;
     30 defparam pll_inst.DIVR = 4'b0000;
     31 defparam pll_inst.DIVF = 7'b1000010;
     32 defparam pll_inst.DIVQ = 3'b101;
     33 defparam pll_inst.FILTER_RANGE = 3'b001;
     34 defparam pll_inst.FEEDBACK_PATH = "SIMPLE";
     35 defparam pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
     36 defparam pll_inst.FDA_FEEDBACK = 4'b0000;
     37 defparam pll_inst.SHIFTREG_DIV_MODE = 2'b00;
     38 defparam pll_inst.PLLOUT_SELECT_PORTB = "GENCLK";
     39 defparam pll_inst.ENABLE_ICEGATE_PORTA = 1'b0;
     40 defparam pll_inst.ENABLE_ICEGATE_PORTB = 1'b0;
     41 `else
     42 assign clk12m_out = clk12m_in;
     43 assign clk25m_out = clk12m_in;
     44 `endif
     45 
     46 endmodule