nexys4.sv (1035B)
1 // Copyright 2015, Brian Swetland <swetland@frotz.net> 2 // Licensed under the Apache License, Version 2.0. 3 4 `default_nettype none 5 6 module top( 7 input clk, 8 output reg[15:0]led 9 ); 10 11 wire [15:0]wdata; 12 wire [15:0]waddr; 13 wire [15:0]raddr; 14 wire [15:0]rdata; 15 wire wr; 16 wire rd; 17 18 assign led = raddr; 19 20 sram ram0( 21 .clk(clk), 22 .waddr(waddr), 23 .wdata(wdata), 24 .we(wr), 25 .raddr(raddr), 26 .rdata(rdata), 27 .re(rd) 28 ); 29 30 cpu 31 `ifdef BIGCPU 32 #( 33 .RWIDTH(32), 34 .SWIDTH(5) 35 ) 36 `endif 37 cpu0( 38 .clk(clk), 39 .mem_raddr_o(raddr), 40 .mem_rdata_i(rdata), 41 .mem_waddr_o(waddr), 42 .mem_wdata_o(wdata), 43 .mem_wr_o(wr), 44 .mem_rd_o(rd) 45 ); 46 47 endmodule 48 49 module sram( 50 input clk, 51 input [15:0]waddr, 52 input [15:0]wdata, 53 input [15:0]raddr, 54 output reg [15:0]rdata, 55 input we, 56 input re 57 ); 58 59 reg [15:0]mem[0:4095]; 60 61 always @(posedge clk) begin 62 if (we) 63 mem[waddr[11:0]] <= wdata; 64 if (re) 65 rdata <= mem[raddr[11:0]]; 66 end 67 68 endmodule