gateware

A collection of little open source FPGA hobby projects
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sdram_glue_ecp5.sv (1213B)


      1 // Copyright 2020, Brian Swetland <swetland@frotz.net>
      2 // Licensed under the Apache License, Version 2.0.
      3 
      4 `default_nettype none
      5 
      6 module sdram_glue #(
      7 	parameter AWIDTH = 12,
      8 	parameter DWIDTH = 16,
      9 	parameter CLK_DELAY = 0, // delay clock by 1..128 x 25pS
     10 	parameter CLK_SHIFT = 0  // delay clock by 1/2 cycle
     11 	) (
     12 	input wire clk,
     13 	output wire pin_clk,
     14 	output wire pin_ras_n,
     15 	output wire pin_cas_n,
     16 	output wire pin_we_n,
     17 	output wire [AWIDTH-1:0]pin_addr,
     18 	inout wire [DWIDTH-1:0]pin_data,
     19 	input wire ras_n,
     20 	input wire cas_n,
     21 	input wire we_n,
     22 	input wire [AWIDTH-1:0]addr,
     23 	input wire [DWIDTH-1:0]data_i,
     24 	output wire [DWIDTH-1:0]data_o,
     25 	output wire data_oe
     26 );
     27 
     28 assign pin_ras_n = ras_n;
     29 assign pin_cas_n = cas_n;
     30 assign pin_we_n = we_n;
     31 assign pin_addr = addr;
     32 
     33 wire delay_clk;
     34 
     35 DELAYG #(
     36 	.DEL_MODE("USER_DEFINED"),
     37 	.DEL_VALUE(CLK_DELAY)
     38 	) clock_delay (
     39 	.A(delay_clk),
     40 	.Z(pin_clk)
     41 );
     42 
     43 ODDRX1F clock_ddr (
     44         .Q(delay_clk),
     45         .SCLK(clk),
     46         .RST(0),
     47         .D0(CLK_SHIFT ? 0 : 1),
     48         .D1(CLK_SHIFT ? 1 : 0)
     49 );
     50 
     51 genvar n;
     52 generate
     53 for (n = 0; n < DWIDTH; n++) begin
     54 	BB iobuf (
     55 		.I(data_o[n]),
     56 		.T(~data_oe),
     57 		.O(data_i[n]),
     58 		.B(pin_data[n])
     59 	);
     60 end
     61 endgenerate
     62 
     63 endmodule
     64