wrapper.sv (1303B)
1 2 `default_nettype none 3 4 module top( 5 input wire clk, 6 input wire a, 7 input wire b, 8 input wire c, 9 output wire d 10 ); 11 12 wire reset; 13 wire sdram_clk; 14 wire sdram_ras_n; 15 wire sdram_cas_n; 16 wire sdram_we_n; 17 wire [15:0]sdram_data_i; 18 wire [15:0]sdram_data_o; 19 wire [11:0]sdram_addr; 20 wire [19:0]rd_addr; 21 wire [3:0]rd_len; 22 wire rd_req; 23 wire rd_ack; 24 wire [15:0]rd_data; 25 wire rd_rdy; 26 wire [19:0]wr_addr; 27 wire [15:0]wr_data; 28 wire [3:0]wr_len; 29 wire wr_req; 30 wire wr_ack; 31 32 sdram sdram0( 33 .clk(clk), 34 .reset(reset), 35 .pin_clk(sdram_clk), 36 .pin_ras_n(sdram_ras_n), 37 .pin_cas_n(sdram_cas_n), 38 .pin_we_n(sdram_we_n), 39 .pin_data_i(sdram_data_i), 40 .pin_data_o(sdram_data_o), 41 .pin_addr(sdram_addr), 42 .rd_addr(rd_addr), 43 .rd_len(rd_len), 44 .rd_req(rd_req), 45 .rd_ack(rd_ack), 46 .rd_data(rd_data), 47 .rd_rdy(rd_rdy), 48 .wr_addr(wr_addr), 49 .wr_data(wr_data), 50 .wr_len(wr_len), 51 .wr_req(wr_req), 52 .wr_ack(wr_ack) 53 ); 54 55 synth_input_wrapper #( 56 .WIDTH(83) 57 ) wrap_input ( 58 .clk(clk), 59 .pin_in(a), 60 .pin_valid(b), 61 .din({ reset, sdram_data_i, rd_addr, rd_len, rd_req, 62 wr_addr, wr_data, wr_len, wr_req }) 63 ); 64 65 synth_output_wrapper #( 66 .WIDTH(51) 67 ) wrap_output ( 68 .clk(clk), 69 .dout( { sdram_clk, sdram_ras_n, sdram_cas_n, sdram_we_n, 70 sdram_data_o, sdram_addr, rd_ack, rd_data, rd_rdy, wr_ack }), 71 .pin_capture(c), 72 .pin_out(d) 73 ); 74 75 endmodule