sync_fifo_test.sv (2649B)
1 // Copyright 2020, Brian Swetland <swetland@frotz.net> 2 // Licensed under the Apache License, Version 2.0. 3 4 `default_nettype none 5 6 module testbench( 7 input wire clk, 8 output reg error = 0, 9 output reg done = 0 10 ); 11 12 wire [31:0]wr_data; 13 wire wr_ready; 14 reg wr_valid = 0; 15 16 wire [31:0]rd_data; 17 wire rd_valid; 18 reg rd_ready = 0; 19 20 wire [31:0]chk_data; 21 22 reg [31:0]count = 0; 23 reg [31:0]rd_count = 0; 24 25 // pattern of writes and reads to issue 26 reg[63:0]w0 = 64'b0001011111111000000000000001111111111111111111111111111111111111; 27 reg[63:0]r0 = 64'b0000000000000001111111111000000000000000000000010001111111111111; 28 29 reg[63:0]w1 = 64'b1111100000000000000000000001111111111111111111111111111111111111; 30 reg[63:0]r1 = 64'b1111111111100011111111111111111111111111111111101010011000111111; 31 32 reg[63:0]w2 = 64'b1111111000000000000000010110001111111111111111100000000000000000; 33 reg[63:0]r2 = 64'b1111111111111111111111111111111111111111111000100000011111110000; 34 35 reg[63:0]w3 = 64'b0000000001000100011000010011100000010101111000000101011011000000; 36 reg[63:0]r3 = 64'b0000000001010010100101001101001111010101111111100101010100111111; 37 38 reg[63:0]w4 = 64'b1111100000000000000000000000000000000000000000000000000000000000; 39 reg[63:0]r4 = 64'b1111100000000000000000000000000000000000000000000000000000000000; 40 41 reg[319:0]writes = { w0, w1, w2, w3, w4 }; 42 reg[319:0]reads = { r0, r1, r2, r3, r4 }; 43 44 always_ff @(posedge clk) begin 45 $display("%3d: W(%08x) %s %s --> R(%08x) %s %s C(%08x) RX(%3d)", 46 count, 47 wr_data, wr_valid ? "V" : "-", wr_ready ? "r" : "-", 48 rd_data, rd_valid ? "v" : "-", rd_ready ? "R" : "-", 49 chk_data, rd_count); 50 51 count <= count + 32'd1; 52 writes <= { writes[318:0], 1'b0 }; 53 reads <= { reads[318:0], 1'b0 }; 54 rd_ready <= reads[319]; 55 wr_valid <= writes[319]; 56 57 if (rd_valid & rd_ready) begin 58 rd_count <= rd_count + 32'd1; 59 if (rd_data != chk_data) begin 60 error <= 1; 61 $display("%3d: rd_data(%08x) != chk_data(%08x)", 62 count, rd_data, chk_data); 63 end 64 end 65 66 if (rd_count == 128) done <= 1; 67 if (count == 32'd500) error <= 1; 68 end 69 70 sync_fifo #( 71 .WIDTH(32), 72 .DEPTH(4) 73 ) fifo ( 74 .clk(clk), 75 .wr_data(wr_data), 76 .wr_valid(wr_valid), 77 .wr_ready(wr_ready), 78 .rd_data(rd_data), 79 .rd_valid(rd_valid), 80 .rd_ready(rd_ready) 81 ); 82 83 // write data stream 84 // cue up a new value next clock, whenever 85 // the current value would have been accepted 86 xorshift32 xs32wr ( 87 .clk(clk), 88 .next(wr_valid & wr_ready), 89 .data(wr_data), 90 .reset(0) 91 ); 92 93 // read verification data stream 94 // cue up a new value next clock, whenever 95 // the current value would have been checked 96 xorshift32 xs32rd ( 97 .clk(clk), 98 .next(rd_valid & rd_ready), 99 .data(chk_data), 100 .reset(0) 101 ); 102 103 endmodule