synth_wrapper.sv (812B)
1 // Copyright 2020, Brian Swetland <swetland@frotz.net> 2 // Licensed under the Apache License, Version 2.0. 3 4 // Inspired by Synthesis Harness Input / Output 5 // from Charles LaForest's FPGA Design Elements 6 // http://fpgacpu.ca/fpga/index.html 7 8 `default_nettype none 9 10 module synth_input_wrapper #( 11 parameter WIDTH = 1 12 )( 13 input wire clk, 14 input wire pin_in, 15 input wire pin_valid, 16 (* keep="true" *) output reg [WIDTH-1:0]din = 0 17 ); 18 19 always @(posedge clk) 20 if (pin_valid) 21 din <= { pin_in, din[WIDTH-1:1] }; 22 23 endmodule 24 25 module synth_output_wrapper #( 26 parameter WIDTH = 1 27 )( 28 input wire clk, 29 input wire [WIDTH-1:0]dout, 30 input wire pin_capture, 31 output wire pin_out 32 ); 33 34 (* keep="true" *) reg [WIDTH-1:0]capture; 35 36 always @(posedge clk) 37 if (pin_capture) 38 capture <= dout; 39 40 assign pin_out = ^capture; 41 42 endmodule