ulx3s-sdram.sv (3142B)
1 // Copyright 2020, Brian Swetland <swetland@frotz.net> 2 // Licensed under the Apache License, Version 2.0. 3 4 `default_nettype none 5 6 `define HAS_SDRAM 7 8 module top( 9 input wire clk_25mhz, 10 11 `ifdef HAS_SDRAM 12 output wire [7:0]led, 13 14 output sdram_clk, 15 output sdram_ras_n, 16 output sdram_cas_n, 17 output sdram_we_n, 18 output [14:0]sdram_addr, 19 inout [15:0]sdram_data, 20 21 output sdram_cke, 22 output sdram_cs_n, 23 output [1:0]sdram_dqm, 24 `endif 25 26 output [3:0]gpdi_dn, 27 output [3:0]gpdi_dp // C R G B 28 ); 29 30 `ifdef HAS_SDRAM 31 assign sdram_cke = 1; 32 assign sdram_cs_n = 0; 33 assign sdram_dqm = 2'b00; 34 `endif 35 36 wire clk25m = clk_25mhz; 37 38 `ifdef SLOWCLOCK 39 wire clk100m; 40 pll_25_100 pll( 41 .clk25m_in(clk25m), 42 .clk100m_out(clk100m), 43 .locked() 44 ); 45 wire testclk = clk100m; 46 `else 47 wire clk125m; 48 wire clk250m; 49 pll_25_125_250 pll( 50 .clk25m_in(clk25m), 51 .clk125m_out(clk125m), 52 .clk250m_out(clk250m), 53 .locked() 54 ); 55 wire testclk = clk125m; 56 `endif 57 58 wire r,g,b; 59 60 wire [7:0]red = {8{r}}; 61 wire [7:0]grn = {8{g}}; 62 wire [7:0]blu = {8{b}}; 63 64 wire active; 65 wire hsync; 66 wire vsync; 67 68 dvi_backend dvi0 ( 69 .pixclk(clk25m), 70 .pixclk5x(clk125m), 71 .pin_dvi_dp(gpdi_dp), 72 .pin_dvi_dn(gpdi_dn), 73 .hsync(hsync), 74 .vsync(vsync), 75 .active(active), 76 .red(red), 77 .grn(grn), 78 .blu(blu) 79 ); 80 81 wire [15:0]info; 82 wire info_e; 83 84 reg [10:0]waddr = 11'd0; 85 wire [10:0]waddr_next = (waddr == 11'd1199) ? 11'd0 : (waddr + 11'd1); 86 always_ff @(posedge testclk) begin 87 waddr <= (info_e) ? waddr_next : waddr; 88 end 89 90 display #( 91 .BPP(1), 92 .RGB(1), 93 .WIDE(0), 94 .HEXMODE(1) 95 ) display0 ( 96 .clk(clk25m), 97 .red(r), 98 .grn(g), 99 .blu(b), 100 .hsync(hsync), 101 .vsync(vsync), 102 .active(active), 103 .frame(), 104 .wclk(testclk), 105 `ifdef HAS_SDRAM 106 .waddr({waddr,1'b0}), 107 .wdata(info), 108 .we(info_e) 109 `else 110 .waddr(0), 111 .wdata(16'h0), 112 .we(0) 113 `endif 114 ); 115 116 `ifdef HAS_SDRAM 117 wire [24:0]rd_addr; 118 wire [15:0]rd_data; 119 wire [3:0]rd_len; 120 wire rd_req; 121 wire rd_ack; 122 wire rd_rdy; 123 124 wire [24:0]wr_addr; 125 wire [15:0]wr_data; 126 wire wr_req; 127 wire wr_ack; 128 wire [3:0]wr_len; 129 130 assign led = wr_addr[24:17]; 131 132 testbench #( 133 .BANKBITS(2), 134 .ROWBITS(13), 135 .COLBITS(10) 136 ) test0 ( 137 .clk(testclk), 138 .error(), 139 .done(), 140 141 .rd_addr(rd_addr), 142 .rd_data(rd_data), 143 .rd_len(rd_len), 144 .rd_req(rd_req), 145 .rd_ack(rd_ack), 146 .rd_rdy(rd_rdy), 147 148 .wr_addr(wr_addr), 149 .wr_data(wr_data), 150 .wr_len(wr_len), 151 .wr_req(wr_req), 152 .wr_ack(wr_ack), 153 154 .info(info), 155 .info_e(info_e) 156 ); 157 158 sdram #( 159 .BANKBITS(2), 160 .ROWBITS(13), 161 .COLBITS(10), 162 .T_PWR_UP(25000), 163 .T_RI(750), 164 .T_RCD(3), 165 .CLK_SHIFT(1), 166 .CLK_DELAY(0) 167 ) sdram0 ( 168 .clk(testclk), 169 .reset(0), 170 171 .pin_clk(sdram_clk), 172 .pin_ras_n(sdram_ras_n), 173 .pin_cas_n(sdram_cas_n), 174 .pin_we_n(sdram_we_n), 175 .pin_addr(sdram_addr), 176 .pin_data(sdram_data), 177 178 `ifdef SWIZZLE 179 .rd_addr({rd_addr[7:4],rd_addr[19:8],rd_addr[3:0]}), 180 .wr_addr({wr_addr[7:4],wr_addr[19:8],wr_addr[3:0]}), 181 `else 182 .rd_addr(rd_addr), 183 .wr_addr(wr_addr), 184 `endif 185 186 .rd_data(rd_data), 187 .rd_len(rd_len), 188 .rd_req(rd_req), 189 .rd_ack(rd_ack), 190 .rd_rdy(rd_rdy), 191 192 .wr_data(wr_data), 193 .wr_len(wr_len), 194 .wr_req(wr_req), 195 .wr_ack(wr_ack) 196 ); 197 `endif 198 199 endmodule 200