testvga.sv (780B)
1 // Copyright 2015, Brian Swetland <swetland@frotz.net> 2 // Licensed under the Apache License, Version 2.0. 3 4 `default_nettype none 5 6 `timescale 1ns / 1ps 7 8 `define HEX_PATHS 9 10 module testbench( 11 input clk, 12 output [3:0]vga_red, 13 output [3:0]vga_grn, 14 output [3:0]vga_blu, 15 output vga_hsync, 16 output vga_vsync, 17 output vga_frame, 18 output reg error = 0, 19 output reg done = 0 20 ); 21 22 wire [1:0]red; 23 wire [1:0]grn; 24 wire [1:0]blu; 25 26 vga40x30x2 vga( 27 .clk25m(clk), 28 .red(red), 29 .grn(grn), 30 .blu(blu), 31 .hs(vga_hsync), 32 .vs(vga_vsync), 33 .fr(vga_frame), 34 .active(), 35 .vram_waddr(11'b0), 36 .vram_wdata(16'b0), 37 .vram_we(1'b0), 38 .vram_clk(clk) 39 ); 40 41 assign vga_red = { red, red[0], red[0] }; 42 assign vga_grn = { grn, grn[0], grn[0] }; 43 assign vga_blu = { blu, blu[0], blu[0] }; 44 45 endmodule