vga.sv (2173B)
1 // Copyright 2012, Brian Swetland <swetland@frotz.net> 2 // Licensed under the Apache License, Version 2.0. 3 4 `default_nettype none 5 6 `timescale 1ns/1ns 7 8 // Vert: 2xSync 30xBack 480xData 12xFront -> 524 lines 9 // Horz: 96xSync 48xBack 640xData 16xFront -> 800 pixels 10 // 11 // CLK: 25MHz, px=40nS, line=32uS, frame=16.768mS 12 13 module vga #( 14 parameter BPP = 4 15 )( 16 input wire clk, 17 output wire hs, 18 output wire vs, 19 output wire fr, 20 output wire [BPP-1:0] r, 21 output wire [BPP-1:0] g, 22 output wire [BPP-1:0] b, 23 24 output wire newline, 25 output wire advance, 26 output wire [7:0] line, 27 input wire [(3*BPP)-1:0] pixel 28 ); 29 30 reg hsync = 1'b0; 31 reg vsync = 1'b0; 32 reg frame = 1'b0; 33 reg active = 1'b0; 34 reg startline = 1'b0; 35 reg [9:0] hcount = 10'b0; 36 reg [9:0] vcount = 10'b0; 37 38 reg next_hsync; 39 reg next_vsync; 40 reg next_frame; 41 reg next_active; 42 reg next_startline; 43 reg [9:0] next_hcount; 44 reg [9:0] next_vcount; 45 46 wire [9:0] adjusted_vcount = next_vcount - 10'd32; 47 48 assign hs = hsync; 49 assign vs = vsync; 50 assign fr = frame; 51 assign line = adjusted_vcount[8:1]; 52 assign advance = active; 53 assign newline = startline; 54 55 assign r = active ? pixel[(3*BPP)-1:(2*BPP)] : { BPP { 1'b0 }}; 56 assign g = active ? pixel[(2*BPP)-1:BPP] : { BPP { 1'b0 }}; 57 assign b = active ? pixel[BPP-1:0] : { BPP { 1'b0 }}; 58 59 always_comb begin 60 next_hsync = hsync; 61 next_vsync = vsync; 62 next_frame = 1'b0; 63 next_active = 1'b0; 64 next_startline = 1'b0; 65 next_hcount = 10'd0; 66 next_vcount = 10'd0; 67 68 if (hcount == 10'd799) begin 69 if (vcount == 10'd523) begin 70 next_vcount = 10'd0; 71 next_frame = 1'b1; 72 next_vsync = 1'b0; 73 end else 74 next_vcount = vcount + 10'd1; 75 next_hcount = 10'd0; 76 next_hsync = 1'b0; 77 next_startline = 1'b1; 78 end else begin 79 next_vcount = vcount; 80 next_hcount = hcount + 10'd1; 81 82 if (hcount == 10'd96) 83 next_hsync = 1'b1; 84 85 if (vcount == 10'd2) 86 next_vsync = 1'b1; 87 88 if ((vcount > 30) && (vcount < 511)) 89 if ((hcount > 142) && (hcount < 783)) 90 next_active = 1'b1; 91 end 92 93 end 94 95 always_ff @(posedge clk) begin 96 hsync <= next_hsync; 97 vsync <= next_vsync; 98 frame <= next_frame; 99 active <= next_active; 100 startline <= next_startline; 101 hcount <= next_hcount; 102 vcount <= next_vcount; 103 end 104 105 endmodule