gateware

A collection of little open source FPGA hobby projects
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vga40x30x2.sv (1199B)


      1 // Copyright 2012, Brian Swetland <swetland@frotz.net>
      2 // Licensed under the Apache License, Version 2.0.
      3 
      4 `default_nettype none
      5 
      6 module vga40x30x2 #(
      7 	parameter BPP = 2,
      8 	parameter RGB = 0
      9 )(
     10 	input wire clk25m,
     11 	output wire [BPP-1:0]red,
     12 	output wire [BPP-1:0]grn,
     13 	output wire [BPP-1:0]blu,
     14 	output wire hs,
     15 	output wire vs,
     16 	output wire fr,
     17 	output wire active,
     18 	input wire vram_clk,
     19 	input wire [10:0]vram_waddr,
     20 	input wire [15:0]vram_wdata,
     21 	input wire vram_we
     22 );
     23 
     24 wire newline;
     25 wire advance;
     26 wire [7:0]line;
     27 wire [(3*BPP)-1:0]pixel;
     28 
     29 vga #(
     30 	.BPP(BPP)
     31 	) vga0 (
     32 	.clk(clk25m),
     33 	.hs(hs),
     34 	.vs(vs),
     35 	.fr(fr),
     36 	.r(red),
     37 	.g(grn),
     38 	.b(blu),
     39 	.newline(newline),
     40 	.advance(advance),
     41 	.line(line),
     42 	.pixel(pixel)
     43 	);
     44 
     45 assign active = advance;
     46 
     47 wire [10:0]vram_raddr;
     48 wire [(RGB*8)+7:0]vram_rdata;
     49 
     50 pixeldata #(
     51 	.BPP(BPP),
     52 	.RGB(RGB)
     53 	) pixeldata0 (
     54 	.clk(clk25m),
     55 	.newline(newline),
     56 	.advance(advance),
     57 	.line(line),
     58 	.pixel(pixel),
     59 	.vram_data(vram_rdata),
     60 	.vram_addr(vram_raddr)
     61 	);
     62 
     63 videoram #((RGB*8)+8,11) vram(
     64 	.rclk(clk25m),
     65 	.re(1'b1),
     66 	.rdata(vram_rdata),
     67 	.raddr(vram_raddr),
     68 	.wclk(vram_clk),
     69 	.we(vram_we),
     70 	.wdata(vram_wdata[(RGB*8)+7:0]),
     71 	.waddr(vram_waddr[10:0])
     72 	);
     73 
     74 endmodule