videoram.sv (802B)
1 // Copyright 2012, Brian Swetland <swetland@frotz.net> 2 // Licensed under the Apache License, Version 2.0. 3 // 4 // sync sram with independent read/write addressing 5 6 `default_nettype none 7 8 `timescale 1ns/1ns 9 10 module videoram #(parameter DWIDTH=16, parameter AWIDTH=8) ( 11 input wire wclk, 12 input wire we, 13 input wire [AWIDTH-1:0] waddr, 14 input wire [DWIDTH-1:0] wdata, 15 input wire rclk, 16 input wire re, 17 input wire [AWIDTH-1:0] raddr, 18 output wire [DWIDTH-1:0] rdata 19 ); 20 21 reg [DWIDTH-1:0] mem[0:2**AWIDTH-1]; 22 reg [DWIDTH-1:0] data; 23 24 assign rdata = data; 25 26 `ifdef HEX_PATHS 27 initial $readmemh("hdl/vga/vram.txt", mem); 28 `else 29 initial $readmemh("vram.txt", mem); 30 `endif 31 32 always @(posedge wclk) begin 33 if (we) 34 mem[waddr] <= wdata; 35 end 36 37 always @(posedge rclk) begin 38 if (re) 39 data <= mem[raddr]; 40 end 41 42 endmodule