commit 1e97450d418e9f688eccc4c9cf365a0fd2d6570c
parent 51048b297dd7c584297723aea1c8702a0f9d2647
Author: Brian Swetland <swetland@frotz.net>
Date: Thu, 25 Sep 2014 22:29:10 -0700
tidier tables (in source and output)
Diffstat:
| M | dap.c | | | 17 | ++++++++--------- |
| M | v7debug.h | | | 79 | +++++++++++++++++++++++++++++++++++++++++++++++++------------------------------ |
2 files changed, 57 insertions(+), 39 deletions(-)
diff --git a/dap.c b/dap.c
@@ -238,30 +238,29 @@ void dumptable(DAP *dap, u32 n, u32 base) {
u32 x, addr;
int i;
- printf("TABLE @ %08x\n", base);
+ printf("TABLE @%08x ", base);
if (readinfo(dap, n, addr, &cid, &pid0, &pid1)) {
- printf(" <error reading cid & pid>\n");
+ printf("<error reading cid & pid>\n");
return;
}
if (dap_mem_rd32(dap, n, base + 0xFCC, &memtype)) {
- printf(" <error reading memtype>\n");
+ printf("<error reading memtype>\n");
return;
}
- printf(" CID %08x PID %08x %08d %dKB%s\n", cid, pid1, pid0,
+ printf("CID %08x PID %08x %08x %dKB%s\n", cid, pid1, pid0,
4 * (1 + ((pid1 & 0xF0) >> 4)),
(memtype & 1) ? " SYSMEM": "");
for (i = 0; i < 128; i++) {
if (dap_mem_rd32(dap, n, base + i * 4, &x)) break;
if (x == 0) break;
- addr = base + (x & 0xFFFFF000);
- printf(" %02d: @%08x%s%s\n", i, addr,
- (x & 1) ? " PRESENT" : "", (x & 2) ? " 32bit" : " 16bit");
if ((x & 3) != 3) continue;
+ addr = base + (x & 0xFFFFF000);
if (readinfo(dap, n, addr, &cid, &pid0, &pid1)) {
printf(" <error reading cid & pid>\n");
continue;
}
- printf(" CID %08x PID %08x %08d %dKB%s\n", cid, pid1, pid0,
+ printf(" %02d: @%08x CID %08x PID %08x %08x %dKB\n",
+ i, addr, cid, pid1, pid0,
4 * (1 + ((pid1 & 0xF0) >> 4)));
if (((cid >> 12) & 0xF) == 1) {
dumptable(dap, n, addr);
@@ -310,7 +309,7 @@ int main(int argc, char **argv) {
#if 1
for (n = 0; n < 8; n++) {
x = 0xefefefef;
- dap_mem_rd32(dap, 0, n*4, &x);
+ dap_mem_rd32(dap, 1, 0x80090FE0 + n*4, &x);
printf("%08x: %08x\n", n*4, x);
}
#endif
diff --git a/v7debug.h b/v7debug.h
@@ -1,35 +1,54 @@
-// ARM v7 Debug Interface
+// ARM Debug Interface
// See: Cortex R5 r1p2 TRM
// http://infocenter.arm.com/help/topic/com.arm.doc.ddi0460d/DDI0460D_cortex_r5_r1p2_trm.pdf
-#define V7DBGDIDR 0x000 // Debug ID Register
-#define V7DBGWFAR 0x018 // Watchpoint Fault Address Register
-#define V7DBGVCR 0x01C // Vector Catch Register
-#define V7DBGECR 0x024 // ?
-#define V7DBGDSCCR 0x028 // Debug State Cache Control Register
-#define V7DBGDSMCR 0x02C //XXX
-#define V7DBGDTRRX 0x080 // Data Transfer Register (host->target)
-#define V7DBGITR 0x084 // Instruction Transfer Register
-#define V7DBGDSCR 0x088 // Debug Status and Control Register
-#define V7DBGDTRTX 0x08C // Data Transfer Register (target->host)
-#define V7DBGDRCR 0x090 // Debug Run Control Register
-#define V7DBGPCSR 0x0A0 // ?
-#define V7DBGCIDSR 0x0A4 // ?
-#define V7DBGBVR 0x100 // Breakpoint Value Registers
-#define V7DBGBCR 0x140 // Breakpoint Control Registers
-#define V7DBGWVR 0x180 // Watchpoint Value Registers
-#define V7DBGWCR 0x1C0 // Watchpoint Control Registers
-#define V7DBGOSLAR 0x300 // ?
-#define V7DBGOSLSR 0x304 // Operating System Lock Status Register
-#define V7DBGOSSRR 0x308 // ?
-#define V7DBGPRCR 0x310 // Device Power-Down and Reset Control Register
-#define V7DBGPRSR 0x314 // Device Power-Down and Reset Status Register
-#define V7DBGLAR 0xFB0 // Lock Access Register
-#define V7DBGLSR 0xFB4 // Lock Status Register
-#define V7DBGAUTHSTATUS 0xDB8 // Authentication Status Register
-#define V7DBGDEVID 0xFC8 // Device ID
-#define V7DBGDEVTYPE 0xFCC // Device Type
-#define V7DBGPID0 0xFD0
-#define V7DBGCID0 0xFF0
+#define DBGDIDR 0x000 // Debug ID Register
+#define DBGWFAR 0x018 // Watchpoint Fault Address Register
+#define DBGVCR 0x01C // Vector Catch Register
+#define DBGECR 0x024 // ?
+#define DBGDSCCR 0x028 // Debug State Cache Control Register
+#define DBGDSMCR 0x02C // ?
+#define DBGDTRRX 0x080 // Data Transfer Register (host->target)
+#define DBGITR 0x084 // Instruction Transfer Register
+#define DBGDSCR 0x088 // Debug Status and Control Register
+#define DBGDTRTX 0x08C // Data Transfer Register (target->host)
+#define DBGDRCR 0x090 // Debug Run Control Register
+#define DBGPCSR 0x0A0 // ?
+#define DBGCIDSR 0x0A4 // ?
+#define DBGBVR 0x100 // Breakpoint Value Registers
+#define DBGBCR 0x140 // Breakpoint Control Registers
+#define DBGWVR 0x180 // Watchpoint Value Registers
+#define DBGWCR 0x1C0 // Watchpoint Control Registers
+#define DBGOSLAR 0x300 // ?
+#define DBGOSLSR 0x304 // Operating System Lock Status Register
+#define DBGOSSRR 0x308 // ?
+#define DBGPRCR 0x310 // Device Power-Down and Reset Control Register
+#define DBGPRSR 0x314 // Device Power-Down and Reset Status Register
+#define DBGLAR 0xFB0 // Lock Access Register
+#define DBGLSR 0xFB4 // Lock Status Register
+#define DBGAUTHSTATUS 0xDB8 // Authentication Status Register
+#define DBGDEVID 0xFC8 // Device ID
+#define DBGDEVTYPE 0xFCC // Device Type
+#define DBGPID0 0xFD0
+#define DBGCID0 0xFF0
+
+
+#define CID_ROM_TABLE 0xB105100D
+#define CID_CORESIGHT 0xB105900D
+
+// See: A9 TRM
+#define PID0_DEBUG 0x000BBC09
+
+// See: Zynq TRM
+#define PID0_CTI 0x002BB906
+#define PID0_PTM 0x001BB950
+#define PID0_ETB 0x003BB907
+#define PID0_FTM 0x000C9001
+#define PID0_FUNNEL 0x001BB908
+#define PID0_ITM 0x002BB913
+#define PID0_TPIU 0x004BB912
+// 0x000BB4A9
+// 0x000BB9A0
+// 0x021893B2
