os-workshop

commit 3c27f66863e22f15fd30ab3bfff96039ef76141b
parent 8897b475f5e6ea25faeb55fee64e0528f5709a6a
Author: Brian Swetland <swetland@frotz.net>
Date:   Mon,  9 May 2022 11:09:04 -0700

boot: tidy up

Diffstat:
M
boot/boot.c
 | 
22
+++++++++++-----------

1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/boot/boot.c b/boot/boot.c
@@ -49,7 +49,6 @@ void mach_exception_handler(uint32_t regs[32]) {
 	uint32_t mcause = csr_read(CSR_MCAUSE);
 	uint32_t mstatus = csr_read(CSR_MSTATUS);
 	uint32_t mtval = csr_read(CSR_MTVAL);
-	uint32_t mtinst = 0; //csr_read(CSR_MTINST); // not supported
 
 #if EMULATE_MISSING_CSR_READS
 	// fragile: no mtval on qemu
@@ -57,7 +56,7 @@ void mach_exception_handler(uint32_t regs[32]) {
 
 	if ((mcause == 2) && ((mtval & (~0xFFF00F80)) == 0x00002073)) {
 		uint32_t rd = (mtval >> 7) & 31;
-		xprintf("BAD CSR READ @%08x -> r%u\n", regs[0], rd);
+		xprintf("BAD CSR READ @%08x (%08x) -> x%u\n", regs[0], mtval, rd);
 		regs[rd] = 0xDEADBEEF;
 		regs[0] += 4;
 		return;
@@ -74,8 +73,8 @@ void mach_exception_handler(uint32_t regs[32]) {
 		regs[4], regs[5], regs[6], regs[7], mcause);
 	xprintf("fp %08x s1 %08x a0 %08x a1 %08x  MTVAL   %08x\n",
 		regs[8], regs[9], regs[10], regs[11], mtval);
-	xprintf("a2 %08x a3 %08x a4 %08x a5 %08x  MTINST  %08x\n",
-		regs[12], regs[13], regs[14], regs[15], mtinst);
+	xprintf("a2 %08x a3 %08x a4 %08x a5 %08x\n",
+		regs[12], regs[13], regs[14], regs[15]);
 	xprintf("\n** HALT\n");
 	for (;;) ;
 }
@@ -89,19 +88,13 @@ void start(uint32_t hartid, uint32_t fdt) {
 
 	int qemu = (csr_read(CSR_MVENDORID) == 0);
 
-	// delegate interrupts and exceptions
-	csr_set(CSR_MIDELEG, INT_LIST);
-	csr_set(CSR_MEDELEG, EXC_LIST);
-
-	// set previous status to S_MODE, previous interrupt status ENABLED
-	csr_write(CSR_MSTATUS, (PRIV_S << MSTATUS_MPP_SHIFT) | MSTATUS_MPIE);
-
 	// set mach exception vector and stack pointer
 	csr_write(CSR_MTVEC, ((uintptr_t) mach_exception_entry) );
 
 	// use the free ram below the supervisor entry as our exception stack
 	csr_write(CSR_MSCRATCH, SVC_ENTRY);
 
+
 #if USE_CLINT_TIMER
 #define CLINT_BASE 0x2000000
 #define TIME_TICK 10000000
@@ -130,6 +123,13 @@ void start(uint32_t hartid, uint32_t fdt) {
 		csr_write(CSR_PMPADDR(0), 0xFFFFFFFF);
 	}
 
+	// delegate interrupts and exceptions
+	csr_set(CSR_MIDELEG, INT_LIST);
+	csr_set(CSR_MEDELEG, EXC_LIST);
+
+	// set previous status to S_MODE, previous interrupt status ENABLED
+	csr_write(CSR_MSTATUS, (PRIV_S << MSTATUS_MPP_SHIFT) | MSTATUS_MPIE);
+
 	xprintf("SVC ENTRY @0x%08x\n\n", SVC_ENTRY);
 	enter_mode_s(hartid, fdt, SVC_ENTRY, 0);
 }