os-workshop

commit 49205eea2c24cca81c2bbbbb7686edeb7a6592d7
parent 770df1b47ce3e35effe57ec5bd959e8ca0eaf87c
Author: Brian Swetland <swetland@frotz.net>
Date:   Sat, 14 May 2022 00:34:58 -0700

riscv: adjust SATP register field defines

Diffstat:
M
example/ex20-mmu.c
 | 
2
+-
M
hw/inc/hw/riscv.h
 | 
4
+++-

2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/example/ex20-mmu.c b/example/ex20-mmu.c
@@ -97,7 +97,7 @@ void start(void) {
 	dump_mmu(pt1);
 
 	// enable MMU
-	csr_write(CSR_SATP, 0x80000000 | ((uintptr_t) pt1) >> 12);
+	csr_write(CSR_SATP, SATP_MODE_SV32 | ((uintptr_t) pt1) >> 12);
 	tlb_flush_all();
 	asm volatile ("nop ; nop ; nop ; nop ; nop");
 
diff --git a/hw/inc/hw/riscv.h b/hw/inc/hw/riscv.h
@@ -27,9 +27,11 @@
 
 #define CSR_SATP       0x180 // Supervisor Addr Translation and Protection
 
-#define SATP_ENABLE    0x80000000
+#define SATP_MODE_BARE 0x00000000U
+#define SATP_MODE_SV32 0x80000000U
 #define SATP_ASID_SHIFT 22
 #define SATP_ASID_SIZE  9
+#define SATP_ASID(n)   ((n) << SATP_ASID_SHIFT)
 
 #define CSR_MVENDORID  0xF11 // Vendor ID
 #define CSR_MARCHID    0xF12 // Architecture ID