commit 695273ab769633cb35ba201eb6538884391e6a96
parent 12b2c2692d135d69ec723965c1b7e389e8e959ba
Author: Brian Swetland <swetland@frotz.net>
Date: Sat, 23 Apr 2022 18:47:01 -0700
hw: more riscv header goodness
- defines for MSTATUS and SSTATUS CSR bits
- defines for Interrupt and Trap numbers (for SCAUSE/MCAUSE/etc)
- fix a typo and make csr macros more robust
Diffstat:
| M | hw/inc/hw/riscv.h | | | 65 | +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++------ |
1 file changed, 59 insertions(+), 6 deletions(-)
diff --git a/hw/inc/hw/riscv.h b/hw/inc/hw/riscv.h
@@ -53,26 +53,79 @@
#define CSR_MCYCLE 0xB00 // Machine Cycle Counter
#define CSR_MINSTRET 0xB02 // Machine Instructions Retired
+// CSR_MSTATUS bits
+#define MSTATUS_TSR 0x00400000U // Trap SRET
+#define MSTATUS_TW 0x00200000U // Timeout Wait (trap on WFI)
+#define MSTATUS_TVM 0x00100000U // Trap Virtual Memory
+#define MSTATUS_MPRV 0x00020000U // Modify PRiVilege
+#define MSTATUS_MPP 0x00001800U // Mode M Prev Priv Mode
+#define MSTATUS_MPIE 0x00000080U // Mode M Prev IRQ Enable
+#define MSTATUS_MIE 0x00000008U // Mode M IRQ Enable
+
+#define MSTATUS_MPP_SHFIT 11
+
+// CSR_STATUS (and CSR_MSTATUS) bits
+#define SSTATUS_SD 0x80000000U // Some Dirty (XS or FS are nonzero)
+#define SSTATUS_MXR 0x00080000U // Make eXecutable Readable (MMU)
+#define SSTATUS_SUM 0x00040000U // Supervisor User Memory access permitted
+#define SSTATUS_XS 0x00018000U // Extension State
+#define SSTATUS_FS 0x00006000U // FP State
+#define SSTATUS_SPP 0x00000100U // Mode S Prev Priv Mode
+#define SSTATUS_UBE 0x00000040U // User Big Endian
+#define SSTATUS_SPIE 0x00000020U // Mode S Prev IRQ Enable
+#define SSTATUS_SIE 0x00000002U // Mode S IRQ Enable
+
+#define SSTATUS_XS_SHIFT 15
+#define SSTATUS_FS_SHIFT 13
+
+// Privilege Levels
+#define PRIV_U 0 // User
+#define PRIV_S 1 // Supervisor
+#define PRIV_M 3 // Machine
+
+// Interrupt numbers (xCAUSE) or bits (xIE/xIP/MIDELEG)
+#define INT_SVC_SW 1
+#define INT_MACH_SW 3
+#define INT_SVC_TIMER 5
+#define INT_MACH_TIMER 7
+#define INT_SVC_EXTERN 9
+#define INT_MACH_EXTERN 11
+
+// Exception numbers (xCAUSE) or bits (MEDELEG)
+#define EXC_INSTR_ADDR_MISALIGN 0
+#define EXC_INSTR_ACCES_FAULT 1
+#define EXC_ILLEGAL_INSTR 2
+#define EXC_BREAKPOINT 3
+#define EXC_LOAD_ADDR_MISALIGN 4
+#define EXC_LOAD_ADDR_FAULT 5
+#define EXC_STORE_ADDR_MISALIGN 6
+#define EXC_STORE_ADDR_FAULT 7
+#define EXC_ECALL_UMODE 8
+#define EXC_ECALL_SMODE 9
+#define EXC_ECALL_MMODE 11
+#define EXC_INSTR_PAGE_FAULT 12
+#define EXC_LOAD_PAGE_FAULT 13
+#define EXC_STORE_PAGE_FAULT 15
// inline assembly helpers for CSR access, etc
#ifndef __ASSEMBLER__
#include <stdint.h>
-#define S(x) #x
+#define __S(x) #x
#define csr_read(csr) ({ \
- uint32_t v; asm volatile ("csrr %0, " S(csr) : "=r"(v)); v; })
+ uint32_t v; asm volatile ("csrr %0, " __S(csr) : "=r"(v)); v; })
#define csr_write(csr, val) ({ \
- asm volatile ("csrw " S(csr) ", %0" :: "rK"(val)) });
+ asm volatile ("csrw " __S(csr) ", %0" :: "rK"(val)); });
#define csr_swap(csr, val) ({ \
- uint32_t v; asm volatile ("csrrw %0, " S(csr) ", %1" : "=r"(v) : "rK"(val)); v; })
+ uint32_t v; asm volatile ("csrrw %0, " __S(csr) ", %1" : "=r"(v) : "rK"(val)); v; })
#define csr_set(csr, bit) ({ \
- uint32_t v; asm volatile ("csrrs %0, " S(csr) ", %1" : "=r"(v) : "rK"(bit)); v; })
+ uint32_t v; asm volatile ("csrrs %0, " __S(csr) ", %1" : "=r"(v) : "rK"(bit)); v; })
#define csr_clr(csr, bit) ({ \
- uint32_t v; asm volatile ("csrrc %0, " S(csr) ", %1" : "=r"(v) : "rK"(bit)); v; })
+ uint32_t v; asm volatile ("csrrc %0, " __S(csr) ", %1" : "=r"(v) : "rK"(bit)); v; })
#endif
