commit 7f131a68cdeb3babc153df74f5950506c15e07a7
parent b32dfcd67f03d2f06b71d25833588330baf18f89
Author: Brian Swetland <swetland@frotz.net>
Date: Wed, 4 May 2022 16:54:59 -0700
hw: add/update platform and cpu headers
Diffstat:
5 files changed, 124 insertions(+), 1 deletion(-)
diff --git a/hw/inc/hw/litex.h b/hw/inc/hw/litex.h
@@ -0,0 +1,33 @@
+
+#pragma once
+
+// Litex UART Registers
+
+#define LX_UART_TX 0x000 // write to transmit
+#define LX_UART_RX 0x000 // read to receive
+#define LX_UART_TXFULL 0x004 // 1 if TX full
+#define LX_UART_RXEMPTY 0x008 // 1 if RX empty
+#define LX_UART_EV_STATUS 0x00C // active events
+#define LX_UART_EV_PENDING 0x010 // pending events (write to clear)
+#define LX_UART_EV_ENABLE 0x014 // events that cause IRQs when pending
+#define LX_UART_TXEMPTY 0x018 // 1 if TX empty
+#define LX_UART_RXFULL 0x01C // 1 if RX full
+#define LX_UART_MAX 0x100
+
+#define LX_UART_EVb_TX (1U << 0) // ready for tx write
+#define LX_UART_EVb_RX (1U << 1) // ready for rx read
+
+
+// Litex Timer Registers
+
+#define LX_TIMER_LOAD 0x000 // write to set value
+#define LX_TIMER_RELOAD 0x004 // value becomes this on underflow
+#define LX_TIMER_EN 0x008 // write 1 to start 0 to stop
+#define LX_TIMER_UPDATE_VALUE 0x00C // write 1 to latch value for reading
+#define LX_TIMER_VALUE 0x010 // ro: last latched value
+#define LX_TIMER_EV_STATUS 0x014 // active events
+#define LX_TIMER_EV_PENDING 0x018 // pending events (write to clear)
+#define LX_TIMER_EV_ENABLE 0x01C // events that cause IRQs when pending
+#define LX_TIMER_MAX 0x100
+
+#define LX_TIMER_EVb_ZERO (1U << 0) // value is zero
diff --git a/hw/inc/hw/platform.h b/hw/inc/hw/platform.h
@@ -0,0 +1,48 @@
+
+#pragma once
+
+#include <hw/riscv.h>
+#include <hw/vexriscv.h>
+
+// Memory Map
+#define DRAM_BASE 0x40000000
+#define DRAM_SIZE (32*1024*1024)
+#define BIOS_SIZE 0x8000
+
+#define TIMER0_BASE 0xF0002000
+#define UART0_BASE 0xF0002800
+
+// Peripheral Interrupt Numbers
+#define TIMER0_IRQn 1
+#define UART0_IRQn 0
+
+// Peripheral Interrupt Bits
+#define TIMER0_IRQb (1U << TIMER0_IRQn)
+#define UART0_IRQb (1U << UART0_IRQn)
+
+#ifndef __ASSEMBLY__
+
+#include <stdint.h>
+
+static inline void io_wr32(uint32_t a, uint32_t v) {
+ *((volatile uint32_t*) a) = v;
+}
+static inline uint32_t io_rd32(uint32_t a) {
+ return *((volatile uint32_t*) a);
+}
+
+static inline void ext_irq_enable(uint32_t bit) {
+ csr_set(CSR_S_INTC_ENABLE, bit);
+}
+static inline void ext_irq_disable(uint32_t bit) {
+ csr_clr(CSR_S_INTC_ENABLE, bit);
+}
+
+static inline int ext_irq_pending(uint32_t bit) {
+ return !!(csr_read(CSR_S_INTC_PENDING) & bit);
+}
+static inline void ext_irq_ack(uint32_t bit) {
+ csr_set(CSR_S_INTC_PENDING, bit);
+}
+
+#endif
diff --git a/hw/inc/hw/riscv.h b/hw/inc/hw/riscv.h
@@ -28,7 +28,7 @@
#define CSR_MVENDORID 0xF11 // Vendor ID
#define CSR_MARCHID 0xF12 // Architecture ID
#define CSR_MIMPID 0xF13 // Implementation ID
-#define CSR_MHARTIT 0xF14 // Hardware Thread ID
+#define CSR_MHARTID 0xF14 // Hardware Thread ID
#define CSR_MCONFIGPTR 0xF15 // Pointer to Config Data Structure
#define CSR_MSTATUS 0x300 // Machine Status
diff --git a/hw/inc/hw/vexriscv.h b/hw/inc/hw/vexriscv.h
@@ -0,0 +1,7 @@
+
+#pragma once
+
+#define CSR_M_INTC_ENABLE 0xBC0
+#define CSR_M_INTC_PENDING 0xFC0
+#define CSR_S_INTC_ENABLE 0x9C0
+#define CSR_S_INTC_PENDING 0xDC0
diff --git a/hw/inc/hw/virtio.h b/hw/inc/hw/virtio.h
@@ -0,0 +1,35 @@
+#pragma once
+
+#include <stdint.h>
+
+#define VIO_MagicValue 0x000 // R
+#define VIO_Version 0x004 // R
+#define VIO_DeviceID 0x008 // R
+#define VIO_VendorID 0x00C // R
+#define VIO_DeviceFeatures 0x010 // R
+#define VIO_DeviceFeaturesSel 0x014 // W
+#define VIO_DriverFeatures 0x020 // W
+#define VIO_DriverFeaturesSel 0x024 // W
+#define VIO_QueueSel 0x030 // W Selects Queue Number for VIO_Queue*
+#define VIO_QueueNumMax 0x034 // R
+#define VIO_QueueNum 0x038 // W
+#define VIO_QueueReady 0x044 // RW
+#define VIO_QueueNotify 0x050 // W
+#define VIO_InterruptStatus 0x060 // R
+#define VIO_InterruptAck 0x064 // W
+#define VIO_DeviceStatus 0x070 // RW
+#define VIO_QueueDescLow 0x080 // W Address of Queue's Descriptor Area
+#define VIO_QueueDescHigh 0x084 // W
+#define VIO_QueueDriverLow 0x090 // W Address of Queue's Driver Area
+#define VIO_QueueDriverHigh 0x094 // W
+#define VIO_QueueDeviceLow 0x0A0 // W Address of Queue's Device Area
+#define VIO_QueueDeviceHigh 0x0A4 // W
+#define VIO_ConfigGeneration 0x0FC // R
+#define VIO_Config 0x100 // RW Device-Specific Config Space
+
+
+#define VIO_MAGIC 0x74726976
+
+// for VIO_Interrupt{Status,Ack}
+#define VIO_INT_USED_BUFFER (1U << 0)
+#define VIO_INT_CONFIG_CHANGED (1U << 1)
