os-workshop

commit b8b0952792447e6754a831e0d8f140e4e261de8d
parent 727b47915b7d4d76ed69d6d8c8b13a232b3fb8b6
Author: Brian Swetland <swetland@frotz.net>
Date:   Fri, 20 May 2022 01:27:41 -0700

boot: fix some bugs in the debug monitor

- initialize STOP properly
- handle both \r and \n as ENTER
- make rd32safe/rd8safe actually safe
 (vexriscv does not allow readback of MSTATUS)

Diffstat:
M
boot/boot.c
 | 
11
++++++++---
M
boot/helpers.S
 | 
24
++++++++----------------

2 files changed, 16 insertions(+), 19 deletions(-)
diff --git a/boot/boot.c b/boot/boot.c
@@ -14,7 +14,7 @@
 #include "boot.h"
 
 eframe_t *EF;
-volatile int STOP;
+volatile int STOP = 0;
 
 // we expect the supervisor program to be in memory after the end of the bootloader
 #define SVC_ENTRY (DRAM_BASE + BOOTLOADER_SIZE)
@@ -27,10 +27,15 @@ static char cmdbuf[128];
 static unsigned cmdlen = 0;
 
 void console_char(uint32_t ch) {
-	if ((ch == '\r')) {
+	if ((ch == '\r') || (ch == '\n')) {
 		xputs("\r\n");
 		cmdbuf[cmdlen] = 0;
+		// rd32safe, rd8safe modify MTVEC/MSTATUS
+		// ensure they're saved and restored here
+		uint32_t status = csr_read(CSR_MSTATUS);
 		console_line(cmdbuf);
+		csr_write(CSR_MSTATUS, status);
+		csr_write(CSR_MTVEC, ((uintptr_t) mach_exception_entry) );
 		cmdlen = 0;
 		return;
 	}
@@ -109,7 +114,7 @@ void start(uint32_t hartid, uint32_t fdt) {
 
 	uart_wr(EV_ENABLE, LX_UART_EVb_RX);
 	uart_wr(EV_PENDING, LX_UART_EVb_RX);
-	csr_set(CSR_M_INTC_ENABLE, UART0_IRQb);
+	csr_write(CSR_M_INTC_ENABLE, UART0_IRQb);
 	csr_set(CSR_MIE, INTb_MACH_EXTERN);
 
 	exit_mode_m(hartid, fdt, SVC_ENTRY, 0);
diff --git a/boot/helpers.S b/boot/helpers.S
@@ -6,30 +6,22 @@
 
 .globl rd32safe // (addr)
 rd32safe:
-	csrr t0, mtvec
-	csrr t1, mstatus
-	la t2, rd32fail
-	mv t3, a0
+	la t0, rd32fail
+	mv t1, a0
 	li a0, 0
-	csrw mtvec, t2
-	lw a0, 0(t3)
-rd32fail:
 	csrw mtvec, t0
-	csrw mstatus, t1
+	lw a0, 0(t1)
+rd32fail:
 	ret
 
 .globl rd8safe // (addr)
 rd8safe:
-	csrr t0, mtvec
-	csrr t1, mstatus
-	la t2, rd8fail
-	mv t3, a0
+	la t0, rd8fail
+	mv t1, a0
 	li a0, 0
-	csrw mtvec, t2
-	lbu a0, 0(t3)
-rd8fail:
 	csrw mtvec, t0
-	csrw mstatus, t1
+	lbu a0, 0(t1)
+rd8fail:
 	ret