os-workshop

commit b8e8a89224f5f477ef09963325aadbeb974cff35
parent 4092b1573f340bed550e20c77bf09e1fb5ad0992
Author: Brian Swetland <swetland@frotz.net>
Date:   Sat, 21 May 2022 16:26:42 -0700

hw/litex: add ethmac registers, base, irq, etc

Diffstat:
M
hw/inc/hw/litex.h
 | 
33
+++++++++++++++++++++++++++++++++
M
hw/inc/hw/platform.h
 | 
7
+++++++

2 files changed, 40 insertions(+), 0 deletions(-)
diff --git a/hw/inc/hw/litex.h b/hw/inc/hw/litex.h
@@ -61,3 +61,36 @@
 #define LX_VTG_VSYNC_START   0x008
 #define LX_VTG_VSYNC_END     0x00C
 #define LX_VTG_VSCAN         0x010
+
+
+// Litex Ethernet MAC
+
+// WR is from MAC to SRAM (RX Packets)
+#define LX_ETHMAC_WR_SLOT       0x000
+#define LX_ETHMAC_WR_LEN        0x004
+#define LX_ETHMAC_WR_ERR        0x008
+#define LX_ETHMAC_WR_EV_STATUS  0x00C
+#define LX_ETHMAC_WR_EV_PENDING 0x010
+#define LX_ETHMAC_WR_EV_ENABLE  0x014
+
+// RD is from SRAM to MAC (TX Packets)
+#define LX_ETHMAC_RD_START      0x018
+#define LX_ETHMAC_RD_READY      0x01C
+#define LX_ETHMAC_RD_LEVEL      0x020
+#define LX_ETHMAC_RD_SLOT       0x024
+#define LX_ETHMAC_RD_LEN        0x028
+#define LX_ETHMAC_RD_EV_STATUS  0x02C
+#define LX_ETHMAC_RD_EV_PENDING 0x030
+#define LX_ETHMAC_RD_EV_ENABLE  0x034
+
+#define LX_ETHMAC_PRE_CRC       0x038
+#define LX_ETHMAC_RX_PRE_ERR    0x03C
+#define LX_ETHMAC_RX_CRC_ERR    0x040
+
+#define LX_ETHMAC_EVb_WR 1
+#define LX_ETHMAC_EVb_RD 1
+
+// Litex Ethernet PHY
+
+#define LX_ETHPHY_RESET      0x000
+
diff --git a/hw/inc/hw/platform.h b/hw/inc/hw/platform.h
@@ -9,6 +9,10 @@
 #define FRAMEBUFFER_BASE   0x40C00000 // default fb dma base
 #define DRAM_SIZE          (32*1024*1024)
 #define BOOTLOADER_SIZE    0x00008000
+#define ETHMAC_SRAM_BASE   0xE0000000
+#define ETHMAC_SLOT_SIZE   0x800
+#define ETHMAC_RX_SLOTS    2
+#define ETHMAC_TX_SLOTS    2
 #define MMIO_BASE          0xF0000000
 
 // MMIO Devices
@@ -22,14 +26,17 @@
 #define SPIFLASH_CORE_BASE 0xF0004000
 #define SPICLASH_PHY_BASE  0xF0004800
 #define SPISDCARD_BASE     0xF0005000
+#define ETHMAC_BASE        0xF0005800
 
 // Peripheral Interrupt Numbers
 #define TIMER0_IRQn 0
 #define UART0_IRQn  1
+#define ETHMAC0_IRQn 2
 
 // Peripheral Interrupt Bits
 #define TIMER0_IRQb (1U << TIMER0_IRQn)
 #define UART0_IRQb (1U << UART0_IRQn)
+#define ETHMAC0_IRQb (1U << ETHMAC_IRQn)
 
 #ifndef __ASSEMBLY__