os-workshop

commit fa5cdd06664c6315326d25558c679d8255323191
parent 3dcb05e2f4bc5ffc956a473bdb7324762514aa2f
Author: Brian Swetland <swetland@frotz.net>
Date:   Thu, 12 May 2022 11:08:54 -0700

docs: fix typo

Diffstat:
M
docs/riscv-assembly.md
 | 
2
+-

1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/riscv-assembly.md b/docs/riscv-assembly.md
@@ -30,7 +30,7 @@ The core 32bit integer instruction set for RISCV is pretty small:
 | beq rs1, rs2, addr | branch if equal | if rs1 == rs2 then pc = addr [2] |
 | bne rs1, rs2, addr | branch if not equal | if rs1 != rs2 then pc = addr [2] |
 | blt rs1, rs2, addr | branch if less than| if rs1 < rs2 then pc = addr [2] |
-| blt rs1, rs2, addr | branch if less than (unsigned) | if rs1 < rs2 then pc = addr [2] |
+| bltu rs1, rs2, addr | branch if less than (unsigned) | if rs1 < rs2 then pc = addr [2] |
 | bge rs1, rs2, addr | branch if >= | if rs1 >= rs2 then pc = addr [2] |
 | bgeu rs1, rs2, addr | branch if >= (unsigned) | if rs1 >= rs2 then pc = addr [2] |
 | lw rd, s12(rs1) | load word | rd = *((u32*) (rs1 + s12)) |