riscv

commit 09a30ddcb38024ba70fe616cc6669f2a448bf2fa
parent 0d4b70e1e805f3cc6c85846f43cabdfcc31b8a36
Author: Brian Swetland <swetland@frotz.net>
Date:   Mon, 21 Oct 2019 20:58:57 -0700

rvsim: fix OC_OP_IMM

- passing 27 tests

Diffstat:
M
rvsim.c
 | 
4
++--

1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/rvsim.c b/rvsim.c
@@ -174,9 +174,9 @@ void rvsim(rvstate_t* s) {
 			}
 		case OC_OP: {
 			uint32_t a = RdR1();
-			uint32_t b = RdR1();
+			uint32_t b = RdR2();
 			uint32_t n;
-			if (ins & 0xDE000000) goto inval;
+			if (ins & 0xBE000000) goto inval;
 			switch (get_fn3(ins) | (ins >> 27)) {
 			case F3_ADD: n = a + b; break;
 			case F3_SLL: n = a << (b & 31); break;