riscv

commit c3f5225d73bf7c13da7c19819d9457941f483932
parent 57b94bbef54f3150c6f65fedd0900fbdc1359b54
Author: Brian Swetland <swetland@frotz.net>
Date:   Tue, 22 Oct 2019 18:19:40 -0700

rvsim: more fixes

- jalr clears bit0
- jalr now avoids tangling up link and addr registers if same
- don't trace writes to x0/zero (nop)

Diffstat:
M
rvsim.c
 | 
10
+++++++---

1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/rvsim.c b/rvsim.c
@@ -110,9 +110,11 @@ static inline void wreg(rvstate_t* s, uint32_t n, uint32_t v) {
 #define trace_reg(fmt...) printf(fmt...)
 
 #define trace_reg_wr(v) do {\
+	uint32_t r = get_rd(ins); \
+	if (r) { \
 	printf("          (%s = %08x)\n", \
 		rvregname(get_rd(ins)), v); \
-	} while (0)
+	}} while (0)
 
 #define trace_mem_wr(a, v) do {\
 	printf("          ([%08x] = %08x)\n", a, v);\
@@ -249,12 +251,14 @@ void rvsim(rvstate_t* s) {
 			if (p) next = pc + get_ib(ins);
 			break;
 			}
-		case OC_JALR:
+		case OC_JALR: {
+			uint32_t a = (RdR1() + get_ii(ins)) & 0xFFFFFFFE;
 			if (get_fn3(ins) != 0) goto inval;
 			WrRd(next);
 			trace_reg_wr(next);
-			next = RdR1() + (get_ii(ins) << 1);
+			next = a;
 			break;
+			}
 		case OC_JAL:
 			WrRd(next);
 			trace_reg_wr(next);