xv6

commit eadbd55af2b5d5a7e20f9b6803686ceed01f43ec
parent c2258bf4d249c34f26a4ed3c2d6ced81744c654e
Author: rsc <rsc>
Date:   Thu, 20 Dec 2007 18:27:07 +0000

oops - wrong bit (vic zandy)

Diffstat:
M
ioapic.c
 | 
2
+-

1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/ioapic.c b/ioapic.c
@@ -17,7 +17,7 @@
 // The first (low) register in a pair contains configuration bits.
 // The second (high) register contains a bitmask telling which
 // CPUs can serve that interrupt.
-#define INT_DISABLED   0x00100000  // Interrupt disabled
+#define INT_DISABLED   0x00010000  // Interrupt disabled
 #define INT_LEVEL      0x00008000  // Level-triggered (vs edge-)
 #define INT_ACTIVELOW  0x00002000  // Active low (vs high)
 #define INT_LOGICAL    0x00000800  // Destination is CPU id (vs APIC ID)