README (2548B)
1 2 This is a collection of tools, scripts, verilog, etc, for experimenting 3 with the Xilinx Zynq SoC FPGA, particularly around using a commandline 4 workflow and avoiding the IPI (IP Integrator) workflow. 5 6 An earlier version that attempted to make use of IPI from the commandline 7 lives in the deprecated-ipi branch. 8 9 Warning: This is very much a work in progress. 10 11 Projects 12 -------- 13 zybo-hdmi - display a test pattern ZYBO board's HDMI output 14 zybo-hdmi-axi - same, but add an axi slave to adjust the pattern 15 zybo-simple-io - AXI access to the switches, buttons, and LEDs 16 ... 17 18 Repository Layout 19 ----------------- 20 hdl/... - verilog, systemverilog, and xdc sources 21 build/... - makefiles and tcl scripts 22 23 Generated Files 24 --------------- 25 sim/${name}-vsim/... - where Verilator intermediates are generated 26 sim/${name}-xsim/... - where Xilinx Xsim intermediates are generated 27 synth/${name}/... - where Vivado synthesis intermediates are generated 28 out/... - where FPGA final products (bitfiles/etc) end up 29 out/${name}.bit - bitfile for project name 30 31 Build System Notes 32 ------------------ 33 34 1. Declare the name of the module and its sources (.v, .sv, .hex): 35 36 MODULE_NAME := ... 37 MODULE_SRCS := ... 38 39 2. invoke the appropriate build rules for the module type: 40 41 include build/vivado-bitfile.mk 42 - create Xilinx out/$(MODULE_NAME).bit bitfile 43 - target device MODULE_PART 44 - required: a top level module named top 45 - to build: make modulename 46 47 include build/verilator-sim.mk 48 - create Verilator simulation target 49 - required: a top level module named testbench(input clk) 50 - provided: clock signal 51 - to run: make modulename-vsim 52 53 include build/vivado-xsim.mk 54 - create Vivado Xsim simulation target 55 - required: a top level module named testbench 56 - to run: make modulename-xsim 57 58 Tools 59 ----- 60 build/mkzynq.go - Generates useful wrappers around Zynq PS7 macro 61 62 Customizing for your Install 63 ---------------------------- 64 build/init.mk should point to Xilinx Vivado, Xilinx SDK, and Verilator. 65 The default setup assumes you installed the 2014.2 version of the Xilinx 66 tools under /work/xilinx/... and built verilator under /work/verilator/... 67 68 Building Verilator 69 ------------------ 70 You can replace /work with some other convenient directory if you like 71 (but be sure to update build/init.mk): 72 0. install autoconf, bison, flex 73 1. cd /work 74 2. git clone http://git.veripool.org/git/verilator 75 3. cd verilator 76 4. autoconf 77 5. ./configure 78 6. make -j32 79 7. you do not need to make install