zynq-sandbox

old FPGA projects for ZYNQ
git clone http://frotz.net/git/zynq-sandbox.git
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build-bitfile.tcl (880B)


      1 
      2 source config.tcl
      3 
      4 synth_design -top top -part $PART
      5 
      6 write_checkpoint -force ./post-synth-checkpoint.dcp
      7 report_utilization -file ./post-synth-utilization.txt
      8 report_timing -sort_by group -max_paths 5 -path_type summary -file ./post-synth-timing.txt
      9 
     10 opt_design
     11 power_opt_design
     12 place_design
     13 write_checkpoint -force ./post-place-checkpoint.dcp
     14 
     15 phys_opt_design
     16 route_design
     17 write_checkpoint -force ./post-route-checkpoint.dcp
     18 
     19 report_utilization -file ./post-route-utilization.txt
     20 report_timing_summary -file ./post-route-timing-summary.txt
     21 report_timing -sort_by group -max_paths 100 -path_type summary -file ./post-route-timing.txt
     22 report_drc -file ./post-route-drc.txt
     23 write_verilog -force ./post-route-netlist.v
     24 write_xdc -no_fixed_only -force ./post-route-constr.xdc
     25 
     26 set_property BITSTREAM.GENERAL.COMPRESS True [current_design]
     27 write_bitstream -force -bin_file $BITFILE
     28