zynq-sandbox

old FPGA projects for ZYNQ
git clone http://frotz.net/git/zynq-sandbox.git
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init.mk (674B)


      1 ## Copyright 2014 Brian Swetland <swetland@frotz.net>
      2 ##
      3 ## Licensed under the Apache License, Version 2.0 
      4 ## http://www.apache.org/licenses/LICENSE-2.0
      5 
      6 VERILATOR := verilator
      7 
      8 VIVADOPATH := /work/xilinx/Vivado/2018.2
      9 XSDKPATH := /work/xilinx/SDK/2018.2
     10 
     11 VIVADO := $(VIVADOPATH)/bin/vivado
     12 XELAB := $(VIVADOPATH)/bin/xelab
     13 XSIM := $(VIVADOPATH)/bin/xsim
     14 XMD := $(XSDKPATH)/bin/xmd
     15 
     16 ifeq ("$(VERBOSE)","")
     17 # reduce the firehose of output chatter from Vivado
     18 VIVADO_FILTER := | grep -e "^INFO:.*Inferred" -e "^WARNING:" -e "^ERROR:"
     19 VIVADO_FILTER += | grep -v '\[Board 49-26\]'
     20 endif
     21 
     22 ALL_TARGETS :=
     23 
     24 # default: assume build is adjacent to top level Makefile
     25 BUILD ?= build