zynq-sandbox

old FPGA projects for ZYNQ
git clone http://frotz.net/git/zynq-sandbox.git
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verilator-sim.mk (1420B)


      1 ## Copyright 2014 Brian Swetland <swetland@frotz.net>
      2 ##
      3 ## Licensed under the Apache License, Version 2.0 
      4 ## http://www.apache.org/licenses/LICENSE-2.0
      5 
      6 MODULE_NAME := $(strip $(MODULE_NAME))
      7 ifeq ("$(MODULE_NAME)","")
      8 $(error no module name)
      9 endif
     10 
     11 MODULE_OBJDIR := sim/$(MODULE_NAME)-vsim
     12 MODULE_RUN := $(MODULE_NAME)-vsim
     13 MODULE_BIN := $(MODULE_OBJDIR)/Vtestbench
     14 
     15 MODULE_HEX_SRCS := $(filter %.hex,$(MODULE_SRCS))
     16 MODULE_VLG_SRCS := $(filter-out %.hex,$(MODULE_SRCS))
     17 
     18 MODULE_OPTS := --top-module testbench 
     19 #-Ihdl
     20 MODULE_OPTS += --Mdir $(MODULE_OBJDIR)
     21 MODULE_OPTS += --exe ../../$(BUILD)/testbench.cpp
     22 MODULE_OPTS += --cc
     23 MODULE_OPTS += -DSIMULATION
     24 
     25 MODULE_OPTS += -CFLAGS -DTRACE --trace
     26 
     27 $(MODULE_BIN): _OPTS := $(MODULE_OPTS)
     28 $(MODULE_BIN): _SRCS := $(MODULE_VLG_SRCS)
     29 $(MODULE_BIN): _HEX := $(MODULE_HEX_SRCS)
     30 $(MODULE_BIN): _DIR := $(MODULE_OBJDIR)
     31 $(MODULE_BIN): _NAME := $(MODULE_NAME)
     32 
     33 $(MODULE_BIN): $(MODULE_SRCS) $(MODULE_HEX_SRCS)
     34 	@mkdir -p $(_DIR) bin
     35 	@for hex in $(_HEX) ; do cp $$hex $(_DIR) ; done
     36 	@echo "COMPILE (verilator): $(_NAME)"
     37 	$(VERILATOR) $(_OPTS) $(_SRCS)
     38 	@echo "COMPILE (C++): $(_NAME)"
     39 	@make -C $(_DIR) -f Vtestbench.mk
     40 
     41 $(MODULE_RUN): _BIN := $(MODULE_BIN)
     42 $(MODULE_RUN): _DIR := $(MODULE_OBJDIR)
     43 
     44 $(MODULE_RUN): $(MODULE_BIN)
     45 	@(cd $(_DIR) && ./Vtestbench)
     46 
     47 ALL_TARGETS += $(MODULE_RUN)
     48 TARGET_$(MODULE_RUN)_DESC := "run verilator simulation"
     49 
     50 MODULE_NAME :=
     51 MODULE_SRCS :=