zynq-sandbox

old FPGA projects for ZYNQ
git clone http://frotz.net/git/zynq-sandbox.git
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vivado-bitfile.mk (2618B)


      1 ## Copyright 2014 Brian Swetland <swetland@frotz.net>
      2 ##
      3 ## Licensed under the Apache License, Version 2.0 
      4 ## http://www.apache.org/licenses/LICENSE-2.0
      5 
      6 MODULE_NAME := $(strip $(MODULE_NAME))
      7 ifeq ("$(MODULE_NAME)","")
      8 $(error no module name)
      9 endif
     10 
     11 MODULE_OBJDIR := synth/$(MODULE_NAME)
     12 MODULE_BIT := out/$(MODULE_NAME).bit
     13 MODULE_CFG := $(MODULE_OBJDIR)/config.tcl
     14 
     15 MODULE_HEX_SRCS := $(filter %.hex,$(MODULE_SRCS))
     16 MODULE_XDC_SRCS := $(filter %.xdc,$(MODULE_SRCS))
     17 MODULE_V_SRCS := $(filter %.v,$(MODULE_SRCS))
     18 MODULE_SV_SRCS := $(filter %.sv,$(MODULE_SRCS))
     19 
     20 $(MODULE_CFG): _V := $(MODULE_V_SRCS)
     21 $(MODULE_CFG): _SV := $(MODULE_SV_SRCS)
     22 $(MODULE_CFG): _XDC := $(MODULE_XDC_SRCS)
     23 $(MODULE_CFG): _DIR := $(MODULE_OBJDIR)
     24 $(MODULE_CFG): _PART := $(MODULE_PART)
     25 $(MODULE_CFG): _NAME := $(MODULE_NAME)
     26 $(MODULE_CFG): _OPTS := -I$(VIVADOPATH)/data/verilog/src/xeclib
     27 
     28 $(MODULE_CFG): $(MODULE_SRCS) Makefile
     29 	@echo "LINT (verilator): $(_NAME)"
     30 	@$(VERILATOR) --top-module top --lint-only $(_OPTS) $(_SV) $(_V)
     31 	@mkdir -p $(_DIR)
     32 	@echo "# auto-generated file" > $@
     33 	@echo "set PART {$(_PART)}" >> $@
     34 	@echo "set BITFILE {../../out/$(_NAME).bit}" >> $@
     35 	@for x in $(_V) ; do echo "read_verilog {../../$$x}" ; done >> $@
     36 	@for x in $(_SV) ; do echo "read_verilog -sv {../../$$x}" ; done >> $@
     37 	@for x in $(_XDC) ; do echo "read_xdc {../../$$x}" ; done >> $@
     38 
     39 $(MODULE_BIT): _HEX := $(MODULE_HEX_SRCS)
     40 $(MODULE_BIT): _DIR := $(MODULE_OBJDIR)
     41 $(MODULE_BIT): _NAME := $(MODULE_NAME)
     42 $(MODULE_BIT): $(MODULE_HEX_SRCS) $(MODULE_CFG)
     43 	@echo "SYNTH (vivado): $(_NAME)"
     44 	@mkdir -p $(_DIR) out
     45 	@rm -f $(_DIR)/log.txt
     46 	@for hex in $(_HEX) ; do cp $$hex $(_DIR) ; done
     47 	@(cd $(_DIR) && $(VIVADO) -mode batch -log log.txt -nojournal -source ../../$(BUILD)/build-bitfile.tcl)
     48 
     49 $(MODULE_NAME)-rtl: _HEX := $(MODULE_HEX_SRCS)
     50 $(MODULE_NAME)-rtl: _DIR := $(MODULE_OBJDIR)
     51 $(MODULE_NAME)-rtl: _NAME := $(MODULE_NAME)
     52 $(MODULE_NAME)-rtl: $(MODULE_HEX_SRCS) $(MODULE_CFG)
     53 	@echo "Elaborate (vivado): $(_NAME)"
     54 	@mkdir -p $(_DIR) out
     55 	@rm -f $(_DIR)/log.txt
     56 	@for hex in $(_HEX) ; do cp $$hex $(_DIR) ; done
     57 	@(cd $(_DIR) && $(VIVADO) -log log.rtl.txt -nojournal -source ../../$(BUILD)/elaborate-design.tcl)
     58 
     59 $(MODULE_NAME): $(MODULE_BIT)
     60 
     61 $(MODULE_NAME)-review: _DIR := $(MODULE_OBJDIR)
     62 
     63 $(MODULE_NAME)-review: $(MODULE_BIT)
     64 	@(cd $(_DIR) && $(VIVADO) -nolog -nojournal post-route-checkpoint.dcp)
     65 
     66 
     67 ALL_TARGETS += $(MODULE_NAME)
     68 ALL_TARGETS += $(MODULE_NAME)-review
     69 TARGET_$(MODULE_NAME)_DESC := "build xilinx bitfile"
     70 TARGET_$(MODULE_NAME)-review_DESC := "build bitfile and review in vivado"
     71 
     72 MODULE_NAME :=
     73 MODULE_SRCS :=
     74 MODULE_PART :=