zynq-sandbox

old FPGA projects for ZYNQ
git clone http://frotz.net/git/zynq-sandbox.git
Log | Files | Refs | README

vivado-xsim.mk (2336B)


      1 ## Copyright 2014 Brian Swetland <swetland@frotz.net>
      2 ##
      3 ## Licensed under the Apache License, Version 2.0 
      4 ## http://www.apache.org/licenses/LICENSE-2.0
      5 
      6 MODULE_NAME := $(strip $(MODULE_NAME))
      7 ifeq ("$(MODULE_NAME)","")
      8 $(error no module name)
      9 endif
     10 
     11 MODULE_V_SRCS := $(filter %.v,$(MODULE_SRCS))
     12 MODULE_SV_SRCS := $(filter %.sv,$(MODULE_SRCS))
     13 MODULE_HEX_SRCS := $(filter %.hex,$(MODULE_SRCS))
     14 
     15 ifneq ("$(NS)","")
     16 MODULE_TIME := $(NS)ns
     17 else
     18 MODULE_TIME := 5000ns
     19 endif
     20 
     21 MODULE_DIR := sim/$(MODULE_NAME)-xsim
     22 MODULE_RUN := $(MODULE_NAME)-xsim
     23 MODULE_XELAB := $(MODULE_DIR)/.xelab.done
     24 
     25 MODULE_OPTS := --debug typical --relax
     26 MODULE_OPTS += -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip 
     27 MODULE_OPTS += --snapshot sim
     28 MODULE_OPTS += --prj sim.prj
     29 MODULE_OPTS += xil_defaultlib.testbench xil_defaultlib.glbl
     30 MODULE_OPTS += -d SIMULATION
     31 # blackbox verilog for xilinx fpga-specific macros
     32 MODULE_VOPTS := -I$(VIVADOPATH)/data/verilog/src/xeclib -DSIMULATION
     33 
     34 $(MODULE_XELAB): _DIR := $(MODULE_DIR)
     35 $(MODULE_XELAB): _NAME := $(MODULE_NAME)
     36 $(MODULE_XELAB): _V := $(MODULE_V_SRCS)
     37 $(MODULE_XELAB): _SV := $(MODULE_SV_SRCS)
     38 $(MODULE_XELAB): _OPTS := $(MODULE_OPTS)
     39 $(MODULE_XELAB): _VOPTS := $(MODULE_VOPTS)
     40 
     41 $(MODULE_XELAB): $(MODULE_V_SRCS) $(MODULE_SV_SRCS)
     42 	@mkdir -p $(_DIR)
     43 	@echo "LINT (verilator): $(_NAME)"
     44 	@$(VERILATOR) --lint-only --top-module testbench $(_VOPTS) $(_V) $(_SV)
     45 	@for src in $(_V) ; do echo "verilog xil_defaultlib \"../../$$src\"" ; done > $(_DIR)/sim.prj
     46 	@for src in $(_SV) ; do echo "sv xil_defaultlib \"../../$$src\"" ; done >> $(_DIR)/sim.prj
     47 	@echo 'verilog xil_defaultlib "$(VIVADOPATH)/data/verilog/src/glbl.v"' >> $(_DIR)/sim.prj
     48 	@echo "COMPILE (xelab): $(_NAME)"
     49 	@(cd $(_DIR) && $(XELAB) $(_OPTS))
     50 	@touch $@
     51 
     52 $(MODULE_RUN): _DIR := $(MODULE_DIR)
     53 $(MODULE_RUN): _HEX := $(MODULE_HEX_SRCS)
     54 $(MODULE_RUN): _TIME := $(MODULE_TIME)
     55 
     56 $(MODULE_RUN): $(MODULE_XELAB)
     57 	@for hex in $(_HEX) ; do cp $$hex $(_DIR) ; done
     58 	@echo 'open_vcd' > $(_DIR)/run.tcl
     59 	@echo 'log_vcd' >> $(_DIR)/run.tcl
     60 	@echo 'run $(_TIME)' >> $(_DIR)/run.tcl
     61 	@echo 'close_vcd' >> $(_DIR)/run.tcl
     62 	@echo 'exit' >> $(_DIR)/run.tcl
     63 	@echo 'SIMULATE (xsim): $(_NAME)'
     64 	@(cd $(_DIR) && $(XSIM) -nolog -t run.tcl sim)
     65 
     66 ALL_TARGETS += $(MODULE_RUN)
     67 TARGET_$(MODULE_RUN)_DESC := "run vivado xsim"
     68 
     69 MODULE_NAME :=
     70 MODULE_SRCS :=