axi_dma_reader.sv (2800B)
1 // Copyright 2014 Brian Swetland <swetland@frotz.net> 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 `timescale 1ns / 1ps 16 17 module axi_dma_reader( 18 input clk, 19 axi_ifc.master m, 20 output reg [31:0]o_data, 21 output reg o_valid, 22 input i_start, 23 input i_ready, 24 input [31:0]i_baseaddr, 25 input [15:0]i_burst_count 26 ); 27 28 assign m.awvalid = 0; 29 assign m.wvalid = 0; 30 assign m.awid = 0; 31 assign m.awaddr = 0; 32 assign m.wdata = 0; 33 assign m.wstrb = 0; 34 assign m.bready = 0; 35 assign m.awburst = 0; 36 assign m.awlen = 0; 37 assign m.awsize = 0; 38 assign m.awlock = 0; 39 assign m.wlast = 0; 40 assign m.awcache = 0; 41 42 typedef enum { IDLE, ACTIVE, RADDR, RDATA } rstate_t; 43 rstate_t rstate = IDLE; 44 rstate_t next_rstate; 45 46 reg [31:0]txn_addr; 47 reg [31:0]next_txn_addr; 48 reg [15:0]txn_count; 49 reg [15:0]next_txn_count; 50 51 reg [31:0]next_o_data; 52 reg next_o_valid; 53 reg next_arvalid; 54 reg next_rready; 55 56 assign m.araddr = txn_addr; 57 assign m.arid = 0; 58 assign m.arburst = 1; // INCR 59 assign m.arsize = 2; // 4 bytes 60 assign m.arlen = 15; 61 assign m.arcache = 0; 62 assign m.arlock = 0; 63 64 always_comb begin 65 next_rstate = rstate; 66 next_txn_addr = txn_addr; 67 next_txn_count = txn_count; 68 next_o_data = o_data; 69 next_o_valid = 0; 70 next_arvalid = 0; 71 next_rready = 1; 72 73 case (rstate) 74 IDLE: begin 75 if (i_start) begin 76 next_rstate = ACTIVE; 77 next_txn_addr = { i_baseaddr[31:6], 6'b0 }; 78 next_txn_count = i_burst_count; 79 end 80 end 81 ACTIVE: begin 82 if (next_txn_count == 0) begin 83 next_rstate = IDLE; 84 end else if (i_ready) begin 85 next_rstate = RADDR; 86 next_arvalid = 1; 87 end 88 end 89 RADDR: begin 90 if (m.arready) begin 91 next_rstate = RDATA; 92 next_rready = 1; 93 end else begin 94 next_arvalid = 1; 95 end 96 end 97 RDATA: begin 98 if (m.rvalid) begin 99 next_o_data = m.rdata; 100 next_o_valid = 1; 101 if (m.rlast) begin 102 next_rstate = ACTIVE; 103 next_txn_count = txn_count - 1; 104 next_txn_addr = txn_addr + 64; 105 end else begin 106 next_rready = 1; 107 end 108 end else begin 109 next_rready = 1; 110 end 111 end 112 endcase 113 end 114 115 reg arvalid = 0; 116 reg rready = 0; 117 assign m.arvalid = arvalid; 118 assign m.rready = rready; 119 120 always_ff @(posedge clk) begin 121 rstate <= next_rstate; 122 txn_addr <= next_txn_addr; 123 txn_count <= next_txn_count; 124 o_data <= next_o_data; 125 o_valid <= next_o_valid; 126 arvalid <= next_arvalid; 127 rready <= next_rready; 128 end 129 130 endmodule 131