axi_hp_dma_reader.sv (2462B)
1 // Copyright 2014 Brian Swetland <swetland@frotz.net> 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 `timescale 1ns / 1ps 16 17 module axi_hp_dma_reader( 18 input clk, 19 axi_ifc.reader m, 20 21 // control interface 22 input [31:0]txn_addr, // bits 6:0 ignored 23 input [31:0]txn_count, // bits 6:0 ignored 24 input txn_start, 25 output reg txn_busy = 0, 26 output reg [31:0]cyc_count = 0, 27 28 // data interface 29 output [DWIDTH-1:0]data, 30 output valid, 31 input ready 32 ); 33 34 // TODO: make 32bit work 35 parameter DWIDTH = 64; 36 37 assign m.arid = 0; 38 assign m.arlen = 15; 39 assign m.arsize = 2'b11; // dword 40 assign m.arburst = 2'b01; // incr 41 assign m.arlock = 0; 42 assign m.arcache = 0; 43 44 logic [31:0]cyc_count_next; 45 46 logic txn_busy_next; 47 48 logic [31:0]araddr = 0; 49 logic [31:0]araddr_next; 50 51 logic [15:0]arcount = 0; 52 logic [15:0]arcount_next; 53 54 logic [19:0]rcount = 0; 55 logic [19:0]rcount_next; 56 57 wire arcount_is_zero = (arcount == 0); 58 wire rcount_is_zero = (rcount == 0); 59 60 assign m.araddr = araddr; 61 assign m.arvalid = (~arcount_is_zero); 62 63 assign m.rready = (~rcount_is_zero) & ready; 64 assign data = m.rdata; 65 66 assign valid = (~rcount_is_zero) & m.rvalid; 67 68 always_comb begin 69 cyc_count_next = cyc_count; 70 araddr_next = araddr; 71 arcount_next = arcount; 72 rcount_next = rcount; 73 txn_busy_next = txn_busy; 74 75 if ( m.rready & m.rvalid ) begin 76 rcount_next = rcount - 1; 77 end 78 79 if ( m.arvalid & m.arready) begin 80 arcount_next = arcount - 1; 81 araddr_next = araddr + 128; 82 end 83 84 if (txn_busy) begin 85 cyc_count_next = cyc_count + 1; 86 if (rcount_is_zero & arcount_is_zero) begin 87 txn_busy_next = 0; 88 end 89 end else begin 90 if (txn_start) begin 91 cyc_count_next = 0; 92 araddr_next = { txn_addr[31:7], 7'd0 }; 93 arcount_next = txn_count[22:7]; 94 rcount_next = { txn_count[22:7], 4'd0 }; 95 txn_busy_next = 1; 96 end 97 end 98 end 99 100 always_ff @(posedge clk) begin 101 araddr <= araddr_next; 102 arcount <= arcount_next; 103 rcount <= rcount_next; 104 txn_busy <= txn_busy_next; 105 cyc_count <= cyc_count_next; 106 end 107 108 endmodule