zynq-sandbox

old FPGA projects for ZYNQ
git clone http://frotz.net/git/zynq-sandbox.git
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axi_ifc.sv (2566B)


      1 // Copyright 2014 Brian Swetland <swetland@frotz.net>
      2 //
      3 // Licensed under the Apache License, Version 2.0 (the "License");
      4 // you may not use this file except in compliance with the License.
      5 // You may obtain a copy of the License at
      6 //
      7 //     http://www.apache.org/licenses/LICENSE-2.0
      8 //
      9 // Unless required by applicable law or agreed to in writing, software
     10 // distributed under the License is distributed on an "AS IS" BASIS,
     11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
     12 // See the License for the specific language governing permissions and
     13 // limitations under the License.
     14 
     15 `timescale 1ns/1ps
     16 
     17 interface axi_ifc;
     18 
     19 parameter AWIDTH = 32;
     20 parameter DWIDTH = 32;
     21 parameter IWIDTH = 1;
     22 parameter AXI3 = 0;
     23 
     24 localparam LENMAX = AXI3 ? 3 : 7;
     25 localparam LOCKMAX = AXI3 ? 1 : 0;
     26 localparam SIZEMAX = AXI3 ? 1 : 2;
     27 localparam STRBWIDTH = (DWIDTH == 64) ? 8 : 4;
     28 
     29 logic [IWIDTH-1:0] awid;
     30 logic [AWIDTH-1:0] awaddr;
     31  logic [1:0]awburst;
     32  logic [3:0]awcache;
     33  logic [LENMAX:0]awlen;
     34  logic [SIZEMAX:0]awsize;
     35  logic [LOCKMAX:0]awlock;
     36 logic awvalid;
     37 logic awready;
     38 
     39 logic [DWIDTH-1:0] wdata;
     40 logic [STRBWIDTH-1:0]wstrb;
     41 logic wvalid;
     42 logic wready;
     43  logic wlast;
     44 
     45 logic [IWIDTH-1:0] bid;
     46 logic [1:0] bresp;
     47 logic bvalid;
     48 logic bready;
     49 
     50 logic [IWIDTH-1:0] arid;
     51 logic [AWIDTH-1:0] araddr;
     52  logic [1:0]arburst;
     53  logic [3:0]arcache;
     54  logic [LENMAX:0]arlen;
     55  logic [SIZEMAX:0]arsize;
     56  logic [LOCKMAX:0]arlock;
     57 logic arvalid;
     58 logic arready;
     59 
     60 logic [IWIDTH-1:0] rid;
     61 logic [DWIDTH-1:0] rdata;
     62 logic [1:0] rresp;
     63 logic rvalid;
     64 logic rready;
     65  logic rlast;
     66 
     67 modport master (
     68 	output awid, awaddr, awvalid, wdata, wstrb, wvalid, bready,
     69 	output awburst, awcache, awlen, awsize, awlock, wlast,
     70 	output arid, araddr, arvalid, rready,
     71 	output arburst, arcache, arlen, arsize, arlock,
     72 	input awready, wready, bid, bresp, bvalid,
     73 	input arready, rid, rdata, rresp, rvalid, rlast
     74 );
     75 
     76 modport writer (
     77 	output awid, awaddr, awvalid, wdata, wstrb, wvalid, bready,
     78 	output awburst, awcache, awlen, awsize, awlock, wlast,
     79 	input awready, wready, bid, bresp, bvalid
     80 );
     81 
     82 modport reader (
     83 	output arid, araddr, arvalid, rready,
     84 	output arburst, arcache, arlen, arsize, arlock,
     85 	input arready, rid, rdata, rresp, rvalid, rlast
     86 );
     87 
     88 modport slave (
     89 	input awid, awaddr, awvalid, wdata, wstrb, wvalid, bready,
     90 	input awburst, awcache, awlen, awsize, awlock, wlast,
     91 	input arid, araddr, arvalid, rready,
     92 	input arburst, arcache, arlen, arsize, arlock,
     93 	output awready, wready, bid, bresp, bvalid,
     94 	output arready, rid, rdata, rresp, rvalid, rlast
     95 );
     96 	
     97 endinterface
     98