axi_pattern_writer.sv (2713B)
1 // Copyright 2014 Brian Swetland <swetland@frotz.net> 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 `timescale 1ns/1ps 16 17 module axi_pattern_writer( 18 input trigger, 19 input clk, 20 axi_ifc.master m 21 ); 22 23 parameter ADDR = 32'h00000000; 24 parameter PTTN = 32'h12345678; 25 26 localparam STATE_IDLE = 4'd0; 27 localparam STATE_WADDR = 4'd1; 28 localparam STATE_WDATA = 4'd2; 29 localparam STATE_ACK = 4'd3; 30 31 initial m.awvalid = 0; 32 initial m.wvalid = 0; 33 34 reg [31:0]waddr = ADDR; 35 reg [31:0]wdata = PTTN; 36 reg [31:0]wdata_next; 37 38 reg [3:0]state = STATE_IDLE; 39 reg [3:0]state_next; 40 41 reg awvalid_next; 42 reg wvalid_next; 43 reg bready_next; 44 reg wlast_next; 45 46 reg [3:0]count = 15; 47 reg [3:0]count_next; 48 49 wire count_is_zero = (count == 4'h0); 50 wire count_is_one = (count == 4'h1); 51 52 always_comb begin 53 state_next = state; 54 count_next = count; 55 wdata_next = wdata; 56 awvalid_next = 0; 57 wvalid_next = 0; 58 bready_next = 0; 59 wlast_next = 0; 60 61 case (state) 62 STATE_IDLE: begin 63 if (trigger) begin 64 state_next = STATE_WADDR; 65 awvalid_next = 1; 66 end 67 end 68 STATE_WADDR: begin 69 if (m.awready) begin 70 state_next = STATE_WDATA; 71 wvalid_next = 1; 72 end else begin 73 awvalid_next = 1; 74 end 75 end 76 STATE_WDATA: begin 77 if (count_is_zero) begin 78 if (m.wready) begin 79 state_next = STATE_ACK; 80 bready_next = 1; 81 end else begin 82 wvalid_next = 1; 83 wlast_next = 1; 84 end 85 end else begin 86 wvalid_next = 1; 87 if (m.wready) begin 88 if (count_is_one) begin 89 wlast_next = 1; 90 end 91 count_next = count - 1; 92 wdata_next = { wdata[3:0], wdata[31:4] }; 93 end 94 end 95 end 96 STATE_ACK: begin 97 if (m.bvalid) begin 98 state_next = STATE_IDLE; 99 count_next = 15; 100 wdata_next = 32'h12345678; 101 end else begin 102 bready_next = 1; 103 end 104 end 105 default: state_next = STATE_IDLE; 106 endcase 107 end 108 109 assign m.awid = 0; 110 assign m.awburst = 1; 111 assign m.awcache = 0; 112 assign m.awsize = 2; 113 assign m.awlen = 15; 114 assign m.awlock = 0; 115 116 assign m.awaddr = waddr; 117 assign m.wdata = wdata; 118 assign m.wstrb = 4'b1111; 119 120 always_ff @(posedge clk) begin 121 state <= state_next; 122 count <= count_next; 123 wdata <= wdata_next; 124 m.awvalid <= awvalid_next; 125 m.wvalid <= wvalid_next; 126 m.bready <= bready_next; 127 m.wlast <= wlast_next; 128 end 129 130 assign m.arvalid = 0; 131 132 endmodule