axi_to_reg_x8.sv (3418B)
1 // Copyright 2014 Brian Swetland <swetland@frotz.net> 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 `timescale 1ns / 1ps 16 17 module axi_to_reg_x8( 18 input clk, 19 axi_ifc.slave axi, 20 reg_ifc.master bank0, 21 reg_ifc.master bank1, 22 reg_ifc.master bank2, 23 reg_ifc.master bank3, 24 reg_ifc.master bank4, 25 reg_ifc.master bank5, 26 reg_ifc.master bank6, 27 reg_ifc.master bank7 28 ); 29 30 localparam COUNT = 8; 31 localparam WIDTH = 20; 32 33 wire [WIDTH-1:0]rreg; 34 wire [WIDTH-1:0]wreg; 35 wire [31:0]rdata[0:COUNT-1]; 36 wire [31:0]wdata; 37 wire rd[0:COUNT-1]; 38 wire wr[0:COUNT-1]; 39 40 axi_to_reg_impl #( 41 .R_ADDR_WIDTH(20), 42 .COUNT(8) 43 ) bridge_impl ( 44 .clk(clk), 45 .s(axi), 46 .o_rreg(rreg), 47 .o_wreg(wreg), 48 .o_rd(rd), 49 .o_wr(wr), 50 .i_rdata(rdata), 51 .o_wdata(wdata) 52 ); 53 54 assign bank0.rd = rd[0]; 55 assign bank0.wr = wr[0]; 56 assign bank0.raddr = rreg[$bits(bank0.raddr)-1:0]; 57 assign bank0.waddr = wreg[$bits(bank0.waddr)-1:0]; 58 assign bank0.wdata = wdata[$bits(bank0.wdata)-1:0]; 59 assign rdata[0] = { {32-$bits(bank0.rdata){1'b0}}, bank0.rdata }; 60 61 assign bank1.rd = rd[1]; 62 assign bank1.wr = wr[1]; 63 assign bank1.raddr = rreg[$bits(bank1.raddr)-1:0]; 64 assign bank1.waddr = wreg[$bits(bank1.waddr)-1:0]; 65 assign bank1.wdata = wdata[$bits(bank1.wdata)-1:0]; 66 assign rdata[1] = { {32-$bits(bank1.rdata){1'b0}}, bank1.rdata }; 67 68 assign bank2.rd = rd[2]; 69 assign bank2.wr = wr[2]; 70 assign bank2.raddr = rreg[$bits(bank2.raddr)-1:0]; 71 assign bank2.waddr = wreg[$bits(bank2.waddr)-1:0]; 72 assign bank2.wdata = wdata[$bits(bank2.wdata)-1:0]; 73 assign rdata[2] = { {32-$bits(bank2.rdata){1'b0}}, bank2.rdata }; 74 75 assign bank3.rd = rd[3]; 76 assign bank3.wr = wr[3]; 77 assign bank3.raddr = rreg[$bits(bank3.raddr)-1:0]; 78 assign bank3.waddr = wreg[$bits(bank3.waddr)-1:0]; 79 assign bank3.wdata = wdata[$bits(bank3.wdata)-1:0]; 80 assign rdata[3] = { {32-$bits(bank3.rdata){1'b0}}, bank3.rdata }; 81 82 assign bank4.rd = rd[4]; 83 assign bank4.wr = wr[4]; 84 assign bank4.raddr = rreg[$bits(bank4.raddr)-1:0]; 85 assign bank4.waddr = wreg[$bits(bank4.waddr)-1:0]; 86 assign bank4.wdata = wdata[$bits(bank4.wdata)-1:0]; 87 assign rdata[4] = { {32-$bits(bank4.rdata){1'b0}}, bank4.rdata }; 88 89 assign bank5.rd = rd[5]; 90 assign bank5.wr = wr[5]; 91 assign bank5.raddr = rreg[$bits(bank5.raddr)-1:0]; 92 assign bank5.waddr = wreg[$bits(bank5.waddr)-1:0]; 93 assign bank5.wdata = wdata[$bits(bank5.wdata)-1:0]; 94 assign rdata[5] = { {32-$bits(bank5.rdata){1'b0}}, bank5.rdata }; 95 96 assign bank6.rd = rd[6]; 97 assign bank6.wr = wr[6]; 98 assign bank6.raddr = rreg[$bits(bank6.raddr)-1:0]; 99 assign bank6.waddr = wreg[$bits(bank6.waddr)-1:0]; 100 assign bank6.wdata = wdata[$bits(bank6.wdata)-1:0]; 101 assign rdata[6] = { {32-$bits(bank6.rdata){1'b0}}, bank6.rdata }; 102 103 assign bank7.rd = rd[7]; 104 assign bank7.wr = wr[7]; 105 assign bank7.raddr = rreg[$bits(bank7.raddr)-1:0]; 106 assign bank7.waddr = wreg[$bits(bank7.waddr)-1:0]; 107 assign bank7.wdata = wdata[$bits(bank7.wdata)-1:0]; 108 assign rdata[7] = { {32-$bits(bank7.rdata){1'b0}}, bank7.rdata }; 109 110 endmodule