zynq-sandbox

old FPGA projects for ZYNQ
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eth_crc32.sv (2351B)


      1 `timescale 1ns / 1ps
      2 
      3 module eth_crc32(
      4 	input clk,
      5 	input en,
      6 	input rst,
      7 	input [7:0]dat,
      8 	output [31:0]crc
      9 	);
     10 
     11 reg [31:0]c = 32'hFFFFFFFF;
     12 reg [31:0]nxt;
     13 
     14 wire [7:0]d = { dat[0],dat[1],dat[2],dat[3],dat[4],dat[5],dat[6],dat[7] };
     15 
     16 assign crc = {
     17 	c[0],c[1],c[2],c[3],c[4],c[5],c[6],c[7],
     18 	c[8],c[9],c[10],c[11],c[12],c[13],c[14],c[15],
     19 	c[16],c[17],c[18],c[19],c[20],c[21],c[22],c[23],
     20 	c[24],c[25],c[26],c[27],c[28],c[29],c[30],c[31]
     21 	};
     22 
     23 always_comb begin 
     24 	nxt[0] = c[24]^c[30]^d[0]^d[6];
     25 	nxt[1] = c[24]^c[25]^c[30]^c[31]^d[0]^d[1]^d[6]^d[7];
     26 	nxt[2] = c[24]^c[25]^c[26]^c[30]^c[31]^d[0]^d[1]^d[2]^d[6]^d[7];
     27 	nxt[3] = c[25]^c[26]^c[27]^c[31]^d[1]^d[2]^d[3]^d[7];
     28 	nxt[4] = c[24]^c[26]^c[27]^c[28]^c[30]^d[0]^d[2]^d[3]^d[4]^d[6];
     29 	nxt[5] = c[24]^c[25]^c[27]^c[28]^c[29]^c[30]^c[31]^d[0]^d[1]^d[3]^d[4]^d[5]^d[6]^d[7];
     30 	nxt[6] = c[25]^c[26]^c[28]^c[29]^c[30]^c[31]^d[1]^d[2]^d[4]^d[5]^d[6]^d[7];
     31 	nxt[7] = c[24]^c[26]^c[27]^c[29]^c[31]^d[0]^d[2]^d[3]^d[5]^d[7];
     32 	nxt[8] = c[0]^c[24]^c[25]^c[27]^c[28]^d[0]^d[1]^d[3]^d[4];
     33 	nxt[9] = c[1]^c[25]^c[26]^c[28]^c[29]^d[1]^d[2]^d[4]^d[5];
     34 	nxt[10] = c[2]^c[24]^c[26]^c[27]^c[29]^d[0]^d[2]^d[3]^d[5];
     35 	nxt[11] = c[3]^c[24]^c[25]^c[27]^c[28]^d[0]^d[1]^d[3]^d[4];
     36 	nxt[12] = c[4]^c[24]^c[25]^c[26]^c[28]^c[29]^c[30]^d[0]^d[1]^d[2]^d[4]^d[5]^d[6];
     37 	nxt[13] = c[5]^c[25]^c[26]^c[27]^c[29]^c[30]^c[31]^d[1]^d[2]^d[3]^d[5]^d[6]^d[7];
     38 	nxt[14] = c[6]^c[26]^c[27]^c[28]^c[30]^c[31]^d[2]^d[3]^d[4]^d[6]^d[7];
     39 	nxt[15] = c[7]^c[27]^c[28]^c[29]^c[31]^d[3]^d[4]^d[5]^d[7];
     40 	nxt[16] = c[8]^c[24]^c[28]^c[29]^d[0]^d[4]^d[5];
     41 	nxt[17] = c[9]^c[25]^c[29]^c[30]^d[1]^d[5]^d[6];
     42 	nxt[18] = c[10]^c[26]^c[30]^c[31]^d[2]^d[6]^d[7];
     43 	nxt[19] = c[11]^c[27]^c[31]^d[3]^d[7];
     44 	nxt[20] = c[12]^c[28]^d[4];
     45 	nxt[21] = c[13]^c[29]^d[5];
     46 	nxt[22] = c[14]^c[24]^d[0];
     47 	nxt[23] = c[15]^c[24]^c[25]^c[30]^d[0]^d[1]^d[6];
     48 	nxt[24] = c[16]^c[25]^c[26]^c[31]^d[1]^d[2]^d[7];
     49 	nxt[25] = c[17]^c[26]^c[27]^d[2]^d[3];
     50 	nxt[26] = c[18]^c[24]^c[27]^c[28]^c[30]^d[0]^d[3]^d[4]^d[6];
     51 	nxt[27] = c[19]^c[25]^c[28]^c[29]^c[31]^d[1]^d[4]^d[5]^d[7];
     52 	nxt[28] = c[20]^c[26]^c[29]^c[30]^d[2]^d[5]^d[6];
     53 	nxt[29] = c[21]^c[27]^c[30]^c[31]^d[3]^d[6]^d[7];
     54 	nxt[30] = c[22]^c[28]^c[31]^d[4]^d[7];
     55 	nxt[31] = c[23]^c[29]^d[5];
     56 end
     57 
     58 always @(posedge clk) begin
     59 	if (rst) begin
     60 		c <= 32'hFFFFFFFF;
     61 	end else if (en) begin
     62 		c <= nxt;
     63 	end
     64 end
     65 
     66 endmodule