eth_rmii_bridge.sv (1701B)
1 // Copyright 2014 Brian Swetland <swetland@frotz.net> 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 `timescale 1ns / 1ps 16 17 // connects a rmii_rx to an rmii_tx through a small fifo 18 19 module eth_rmii_bridge( 20 input clk, 21 22 input rxvalid, 23 input [7:0]rxdata, 24 input rxeop, 25 26 output reg txpacket = 0, 27 output [7:0]txdata, 28 input txadvance, 29 input txbusy 30 ); 31 32 wire fifo_valid; 33 wire [8:0]fifo_rdata; 34 reg fifo_rd; 35 reg fifo_err; 36 37 reg txpacket = 0; 38 reg next_txpacket; 39 40 assign txdata = fifo_rdata[7:0]; 41 42 always_comb begin 43 next_txpacket = txpacket; 44 fifo_rd = 0; 45 fifo_err = 0; 46 if (fifo_valid) begin 47 if (txpacket == 0) begin 48 // not transmitting, new SOP 49 if (txbusy == 0) begin 50 next_txpacket = 1; 51 end 52 end else if (fifo_rdata[8]) begin 53 // EOP terminates transmit 54 next_txpacket = 0; 55 fifo_rd = 1; 56 end else if (txadvance) begin 57 fifo_rd = 1; 58 end 59 end else begin 60 fifo_rd = 1; 61 if (txadvance) fifo_err = 1; 62 end 63 end 64 65 always @(posedge clk) begin 66 txpacket <= next_txpacket; 67 end 68 69 70 simple_fifo #(.WIDTH(9)) fifo0( 71 .clk(clk), 72 .wr(rxvalid | rxeop), 73 .wdata({rxeop,rxdata}), 74 .rd(fifo_rd), 75 .rdata(fifo_rdata), 76 .rvalid(fifo_valid), 77 .not_empty(), 78 .not_full() 79 ); 80 81 endmodule